TAS3204PAG

更新时间： 2024-01-13 14:57:22

品牌	Logo	应用领域
德州仪器 - TI		消费电路商用集成电路
页数	文件大小	规格书
72页	1211K
描述
AUDIO DSP WITH ANALOG INTERFACE

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技术参数
数据手册

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TAS3204PAG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	TQFP-64	针数：	64
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks	风险等级：	0.77
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e4
长度：	10 mm	湿度敏感等级：	4
功能数量：	1	端子数量：	64
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装等效代码：	TQFP64,.47SQ	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Other Consumer ICs
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

TAS3204PAG 数据手册

TAS3204

AUDIO DSP

WITH ANALOG INTERFACE

www.ti.com

SLES197–APRIL 2007

–

Sample rate change on the fly should be handled by customer system controller. The TAS3204

device does not include any internal clock error or click/pop detection/management.

Customer-specific DAP filter coefficients must be uploaded by customer system controller on

changing sample rate.

In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz

or 48 kHz.

2.6 I²C Control Interface

The TAS3204 has an I²C slave-only interface (SDA1 and SCL1) for receiving commands and providing

status to the system controller, and a separate master I²C interface (SDA2 and SCL2) to download

programs and data from external memory such as an EEPROM. See Section 6 for more information. I²C

interface is not 5-V tolerant.

2.7 8051 Microcontroller

The 8051 microcontroller receives and distributes I²C write data. It retrieves and outputs data as

requested from the I²C bus controller. It performs most processing tasks requiring multi-frame processing

cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I²C

commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program

cannot be altered. The microcontroller has specialized hardware for a master and slave interface

operation, volume updates, and a programmable interval-timer interrupt.

2.8 Audio Digital Signal Processor Core

The audio digital signal processor core arithmetic unit is a fixed-point computational engine consisting of

an arithmetic unit and data and coefficient memory blocks. The audio processing structure, which can

include mixers, multiplexers, volume, bass and treble, equalizers, dynamic range compression, or

third-party algorithms, is running in the DAP. The 8051 microcontroller has access to DAP resources such

as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The

primary blocks of the audio DSP core are:

•

48-bit data path with 76-bit accumulator

DSP controller

Memory interface

Coefficient RAM (1K×28)

Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48)

Program RAM (3K×55)

The DAP is discussed in detail in the following sections.

Functional Description

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