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TAS3204PAG PDF预览

TAS3204PAG

更新时间: 2024-01-27 19:20:40
品牌 Logo 应用领域
德州仪器 - TI 消费电路商用集成电路
页数 文件大小 规格书
72页 1211K
描述
AUDIO DSP WITH ANALOG INTERFACE

TAS3204PAG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TQFP-64针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:0.77
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G64JESD-609代码:e4
长度:10 mm湿度敏感等级:4
功能数量:1端子数量:64
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP64,.47SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

TAS3204PAG 数据手册

 浏览型号TAS3204PAG的Datasheet PDF文件第1页浏览型号TAS3204PAG的Datasheet PDF文件第2页浏览型号TAS3204PAG的Datasheet PDF文件第4页浏览型号TAS3204PAG的Datasheet PDF文件第5页浏览型号TAS3204PAG的Datasheet PDF文件第6页浏览型号TAS3204PAG的Datasheet PDF文件第7页 
TAS3204  
AUDIO DSP  
WITH ANALOG INTERFACE  
www.ti.com  
SLES197APRIL 2007  
2 Functional Description  
The TAS3204 is an audio system-on-a-chip (SOC) designed for mini/micro systems, multimedia-speaker,  
and MP3 player docking systems. It includes analog interface functions: three multiplex (MUX) stereo  
inputs with two stereo analog-to-digital converters (ADCs), two stereo digital-to-analog converters (DACs)  
with analog outputs consisting of differential stereo line drivers. Four channels of serial digital audio  
processing are also provided. The TAS3204 has a programmable audio digital signal processor (DSP) that  
preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle  
28×48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM.  
The TAS3204 is composed of eight functional blocks:  
1. Analog input/mux/stereo ADC  
2. Two stereo DACs  
3. Analog reference system  
4. Power supply  
5. Clocks, digital pll, and serial data interface  
6. I2C control interface  
7. 8051 microcontroller  
8. Audio DSP – digital audio processing  
DPLL  
Master/Slave  
Oscillator  
512Fs XTAL  
SCL1/SDA1  
SCL2/SDA2  
8051 Microprocessor Core  
Control  
I2C  
Control  
Interface  
Registers  
External  
RAM 2K  
MCLK_IN  
512Fs  
8-Bit  
MCU  
GPIO1/2  
Internal  
Slave  
RAM 256  
Volume  
Update  
Code  
Clock  
Divider  
RAM 16K  
LRCLK_IN  
SCLK_IN  
Clock  
Generation  
DSP  
Control  
Memory  
Interface  
DSP Core  
LRCLK_OUT  
SCLK_OUT  
Coefficient  
RAM 1.2K  
Serial Audio Port  
Input  
Cross  
Bar  
Data RAM  
1K Upper Mem  
768 Lower Mem  
Code  
SDIN1/2  
Data  
Path  
Mixer  
Output Cross  
SDOUT1/2  
Bar Mixer  
RAM 3K  
Two Differential  
Stereo Analog  
Outputs  
Two Stereo  
DAC  
128Fs  
Three  
Differential  
Stereo  
Two Stereo  
ADC  
AVDD  
DVDD  
Power  
Analog Inputs  
Supply  
Legend  
Clocks  
Internal Connection  
External Connection  
Digital Data  
Analog Data  
Figure 2-1. Expanded Functional Block Diagram  
Submit Documentation Feedback  
Functional Description  
3

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