Datasheet > T14L1024A-10D

T14L1024A-10D

更新时间： 2024-11-09 22:40:59

品牌	Logo	应用领域
TMT		/
页数	文件大小	规格书
12页	87K
描述
128K X 8 HIGH SPEED CMOS STATIC RAM

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技术参数
数据手册

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T14L1024A-10D 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

T14L1024A-10D 数据手册

tmCH

Preliminary T14L1024A

128K X 8 HIGH SPEED

CMOS STATIC RAM

SRAM

FEATURES

GENERAL DESCRIPTION

The T14L1024A is a one-megabit density, fast

static random access memory organized as 131,072

words by 8 bits. It is designed for use in high

performance memory applications such as main

memory storage and high speed communication

buffers. Fabricated using high performance CMOS

technology, access times down to 10ns are achieved.

Memory expansion by banking is easily

• Fast Address Access Times : 10/12/15ns

• Single 3.3V ±0.3V power supply

• Low Power Consumption : 110/105/100mA

• TTL I/O compatible

• 2.0V data retention mode

• Automatic power-down when deselected

• Available packages :

accomplished using the chip enable pins CE1 and

CE2. This device is packaged in a standard 32-pin

300 mil DIP/SOJ and 32-pin SOP/TSOP-I.

32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I

• Industry Standard Pin Assignment

BLOCK DIAGRAM

Vcc

Vss

PIN CONFIGURATION

CORE

ARRAY

DECODER

A10

Vcc

A11

CE2

A12

A13

A14

A15

A16

CE1

CE2

I/O0

DIP

SOJ

SOP

DATA I/O

I/O7

PIN DESCRIPTION

A16

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

SYMBOL

DESCRIPTION

A0 - A16

Address Inputs

I/O0 - I/O7

/CE1,CE2

/WE

Data Inputs/Outputs

Chip Select Inputs

Write Enable

I/O0

I/O1

I/O2

Vss

/OE

Vcc

Vss

Output Enable

Power Supply

Ground

A15

A14

A13

A12

CE2

A11

VCC

A10

A16

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

VSS

I/O2

I/O1

I/O0

PART NUMBER EXAMPLES

PACKAGE

SPEED

10ns

T14L1024A-10P TSOP-I 8x13.4mm 10ns

TSOP-I

T14L1024A-10J

SOJ 300mil

T14L1024A-10H

T14L1024A-10N

T14L1024A-10D

TSOP-I 8x20mm 10ns

DIP 300mil

SOP

10ns

TM Technology, Inc. reserves the right

to change products or specifications without notice.

P. 1

Publication Date: SEP. 2002

Revision:0.F

12 3 4 5 6 7...12

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