TE
tmCH
T14M1024A
128K X 8 HIGH SPEED
CMOS STATIC RAM
SRAM
FEATURES
GENERAL DESCRIPTION
The T14M1024A is a one-megabit density, fast
static random access memory organized as 131,072
words by 8 bits. It is designed for use in high
performance memory applications such as main
memory storage and high speed communication
buffers. Fabricated using high performance CMOS
technology, access times down to 10ns are achieved.
Memory expansion by banking is easily
• Fast Address Access Times : 10/12/15ns
• Single 5V +10% power supply
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
accomplished using the chip enable pins CE1 and
CE2. This device is packaged in a standard 32-pin
300 mil SOJ and 32-pin TSOP-I.
32-pin 300 mil SOJ & 32-pin TSOP-I
• Industry Standard Pin Assignment
BLOCK DIAGRAM
PIN CONFIGURATION
Vcc
Vss
CORE
ARRAY
A0
DECODER
.
.
.
NC
A10
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A11
CE2
WE
A12
A13
A14
A15
OE
.
A16
3
CE1
CE2
A8
4
I/O0
A7
5
.
.
.
DATA I/O
A6
6
WE
OE
A5
7
I/O7
SOJ
A4
8
A3
9
A2
10
11
12
13
14
15
16
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTION
A1
A0
SYMBOL
A0 - A16
I/O0 - I/O7
CE1,CE2
WE
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
I/O0
I/O1
I/O2
Vss
Write Enable
Output Enable
OE
Vcc
Vss
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A14
A13
A12
WE
CE2
A11
VCC
NC
A10
A9
Power Supply
Ground
TSOP-I
PART NUMBER EXAMPLES
A8
A7
A6
A5
PACKAGE
SPEED
10ns
A1
A2
A3
T14M1024A-10J SOJ 300mil
A4
T14M1024A-10P TSOP-I 8x13.4mm 10ns
T14M1024A-10H TSOP-I 8x20mm 10ns
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: SEP. 2002
Revision:E