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SY89537LMZTR PDF预览

SY89537LMZTR

更新时间: 2024-11-11 12:58:35
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麦瑞 - MICREL /
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19页 743K
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SY89537LMZTR 数据手册

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SY89537L  
3.3V Precision LVPECL and LVDS  
Programmable Multiple Output Bank Clock  
Synthesizer and Fanout Buffer  
General Description  
The SY89537L integrated programmable clock  
synthesizer and fanout is part of a precision PLL-  
based clock generation family optimized for enterprise  
switch, router, and multiprocessor server applications.  
This family is ideal for generating internal system  
timing requirements up to 700MHz for multiple ASICs,  
FPGAs, and NPUs. These devices integrate the  
following blocks into a single monolithic IC:  
Precision Edge®  
Features  
Integrated programmable synthesizer with multiple  
output dividers, fanout buffers, and clock drivers  
Direct interface to crystal: 14MHz to 18MHz  
Input MUX accepts a reference and a crystal  
PLL (Phase-Lock-Loop) based synthesizer  
Fanout buffers  
(XTAL) source  
– Ideal for reference backup clock source or  
system test frequency source  
– Patent-pending unique input MUX isolates XTAL  
and reference inputs minimizes crosstalk  
Clock generator (dividers)  
Logic translation (LVPECL, LVDS)  
Five independently programmable output  
banks  
Guaranteed AC performance:  
– 87.15MHz to 700MHz output frequency range  
(with RFCK at 16.6MHz)  
– <100psPP total jitter  
– <7psRMS cycle-to-cycle jitter  
– <8psPP deterministic jitter  
This level of integration minimizes additive jitter and  
part-to-part skew associated with discrete alternatives,  
resulting in superior system-level timing with reduced  
board space and power. For applications that require  
a zero-delay function, see the SY89538L.  
All support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
– <0.7psRMS crosstalk induced jitter  
– <50ps bank-to-bank skew  
Output bank synchronization control pin  
LVPECL and LVDS outputs  
TTL/CMOS compatible control logic  
Applications  
Enterprise routers, switches, servers and  
workstations  
Five independently programmable output  
Parallel processor-based systems  
frequency banks:  
Internal system clock generation for ASICs, NPUs,  
– Four differential LVPECL output banks  
– One differential LVDS output bank with 3 output  
pairs  
FPGAs  
Markets  
Separate output enable for each bank  
3.3V ±10% power supply (2.5V output capable)  
LAN/WAN  
Enterprise servers  
Test and measurement  
Guaranteed over the commercial and industrial  
temperature range (-40C to +85C)  
Available in 44-pin (7mm x 7mm) QFN package  
Precision Edge is a registered trademark of Micrel, Inc.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
M9999-121207-B  
hbwhelp@micrel.com or (408) 955-1690  
December 2007  

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