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SY89538LHY PDF预览

SY89538LHY

更新时间: 2024-11-11 19:43:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP 接口集成电路
页数 文件大小 规格书
23页 644K
描述
SPECIALTY INTERFACE CIRCUIT, PQFP64

SY89538LHY 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LEAD FREE, TQFP-64Reach Compliance Code:compliant
风险等级:5.39接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
电源电压1-最大:3.6 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

SY89538LHY 数据手册

 浏览型号SY89538LHY的Datasheet PDF文件第2页浏览型号SY89538LHY的Datasheet PDF文件第3页浏览型号SY89538LHY的Datasheet PDF文件第4页浏览型号SY89538LHY的Datasheet PDF文件第5页浏览型号SY89538LHY的Datasheet PDF文件第6页浏览型号SY89538LHY的Datasheet PDF文件第7页 
SY89538L  
3.3V, Precision LVPECL and LVDS  
Programmable Multiple Output Bank Clock  
Synthesizer and Fanout Buffer with Zero Delay  
General Description  
The SY89538L integrated programmable clock  
synthesizer and fanout is part of a precision PLL-  
based clock generation family optimized for  
enterprise switch, router, and multiprocessor server  
applications. This family is ideal for generating  
internal system timing requirements up to 750MHz for  
multiple ASICs, FPGAs, and NPUs. These devices  
integrate the following blocks into a single monolithic  
IC:  
Precision Edge®  
Features  
Integrated programmable synthesizer with multiple  
output dividers, fanout buffers, and clock drivers  
Zero-delay capability: 29.375MHz to 756MHz  
Reference clock input: 9.325MHz to 756MHz  
PLL (Phase-Lock-Loop) based synthesizer  
Zero-delay MUX and feedback capability  
1:4 LVPECL fanout  
Input MUX accepts a reference and a crystal  
(XTAL) source  
– Ideal for reference backup clock source or  
system test frequency source  
– Patent-pending unique input MUX isolates XTAL  
and reference inputs which minimizes crosstalk  
1:3 LVDS fanout  
Clock generator (dividers)  
Guaranteed AC performance:  
– Output frequency range: 29.375MHz to 756MHz  
– <150psPP total jitter  
Logic translation (LVPECL, LVDS)  
Five-independently programmable output  
banks  
– <6psRMS cycle-to-cycle jitter (XTAL Input)  
– <8psPP deterministic jitter  
This level of integration minimizes additive jitter and  
part-to-part skew associated with discrete  
– <0.7psRMS crosstalk induced jitter  
– <75ps output-to-output skew  
TTL/CMOS-compatible control logic  
Five-independently programmable output  
frequency banks:  
alternatives, resulting in superior system-level timing  
with reduced board space and power. For  
applications that do not require a zero-delay function,  
see the SY89537L.  
All support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
– Four differential LVPECL output banks  
– One differential LVDS output bank with three  
output pairs  
Output bank synchronization control pin  
Output enable  
Applications  
Enterprise routers, switches, servers and  
workstations  
Parallel processor-based systems  
3.3V ±10% power supply (2.5V output capable)  
Internal system clock generation for ASICs, NPUs  
Guaranteed over the industrial temperature range  
and FPGAs  
(-40°C to +85°C)  
Available in a 64-pin EPAD-TQFP  
Markets  
LAN/WAN  
Enterprise servers  
Test and measurement  
Precision Edge is a registered trademark of Micrel, Inc.  
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
M9999-010808-E  
hbwhelp@micrel.com or (408) 955-1690  
January 2008  

SY89538LHY 替代型号

型号 品牌 替代类型 描述 数据表
SY89538LHY-TR MICROCHIP

完全替代

SPECIALTY INTERFACE CIRCUIT, PQFP64

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