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SY89534LHZ-TR PDF预览

SY89534LHZ-TR

更新时间: 2024-11-11 14:36:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
15页 111K
描述
89534 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64

SY89534LHZ-TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LEAD FREE, TQFP-64Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.79
系列:89534输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:64
实输出次数:13最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:OTHER
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm
最小 fmax:500 MHzBase Number Matches:1

SY89534LHZ-TR 数据手册

 浏览型号SY89534LHZ-TR的Datasheet PDF文件第2页浏览型号SY89534LHZ-TR的Datasheet PDF文件第3页浏览型号SY89534LHZ-TR的Datasheet PDF文件第4页浏览型号SY89534LHZ-TR的Datasheet PDF文件第5页浏览型号SY89534LHZ-TR的Datasheet PDF文件第6页浏览型号SY89534LHZ-TR的Datasheet PDF文件第7页 
®
3.3V, PRECISION, 33MHz to 500MHz  
PROGRAMMABLE LVPECL AND  
LVDS BUS CLOCK SYNTHESIZER  
Precision Edge  
SY89534L  
SY89535L  
FEATURES  
Integrated synthesizer plus fanout buffers, clock  
®
dividers, and translator in a single 64-pin package  
Precision Edge  
Accepts any reference input between 14MHz to  
160MHz (single-ended or differential)  
DESCRIPTION  
33MHz to 500MHz output frequency range  
The SY89534L and SY89535L programmable clock  
synthesizersarea3.3V,high-frequency,precisionPLL-based  
family optimized for multi-frequency, large clock-tree  
applications that require the highest precision. These devices  
integrate the following blocks into a single monolithic IC:  
LVPECL outputs (SY89534L)  
LVPECL and LVDS outputs (SY89535L)  
3.3V ±10% power supply  
Low jitter: <50ps cycle-to-cycle  
Low pin-to-pin skew: <50ps  
TTL/CMOS compatible control logic  
• PLL (Phase-Lock-Loop)-based synthesizer  
• Fanout buffer  
• Clock generator (divider)  
• Logic translation (LVPECL, LVDS)  
3 independently programmable output frequency  
banks:  
• 9 differential output pairs @BankB (LVPECL/LVDS)  
• 2 differential output pairs @BankA (LVPECL)  
• 2 differential output pairs @BankC (LVPECL)  
The SY89534L and SY89535L includes a flexible input  
designthatacceptsanyreferenceinput;single-endedLVTTL/  
CMOS, SSTL and differential LVPECL, LVDS, HSTL and  
CML.  
Available in 64-pin EPAD-TQFP  
This level of integration minimizes the additive jitter and  
part-to-part skew associated with the discrete alternative,  
resulting in superior system-level timing as well as reduced  
board space and power. For applications that must interface  
to a crystal oscillator, see the SY89532/33.  
Data sheets and support documentation can be found on  
Micrel’s web site at www.micrel.com.  
PRODUCT SELECTION GUIDE  
APPLICATIONS  
Servers  
Input  
Output  
Workstations  
Device  
Crystal Reference BankA  
BankB  
BankC  
Parallel processor-based systems  
Other high-performance computing  
Communications  
SY89532L*  
SY89533L*  
SY89534L  
SY89535L  
X
X
LVPECL LVPECL LVPECL  
LVPECL LVDS LVPECL  
LVPECL LVPECL LVPECL  
LVPECL LVDS LVPECL  
X
X
*Refer to SY89532/33L data sheet for details.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: E  
Amendment: /0  
M9999-110308  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: November 2008  

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