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SY89536LHC PDF预览

SY89536LHC

更新时间: 2024-09-30 04:30:07
品牌 Logo 应用领域
麦瑞 - MICREL 逻辑集成电路驱动时钟
页数 文件大小 规格书
16页 155K
描述
3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER

SY89536LHC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:HTFQFP,
针数:64Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.92
其他特性:ALSO REQUIRES 1.8V SUPPLY系列:89536
输入调节:DIFFERENTIALJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:64实输出次数:13
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):240认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mm最小 fmax:500 MHz

SY89536LHC 数据手册

 浏览型号SY89536LHC的Datasheet PDF文件第2页浏览型号SY89536LHC的Datasheet PDF文件第3页浏览型号SY89536LHC的Datasheet PDF文件第4页浏览型号SY89536LHC的Datasheet PDF文件第5页浏览型号SY89536LHC的Datasheet PDF文件第6页浏览型号SY89536LHC的Datasheet PDF文件第7页 
3.3V, PRECISION, 33MHz to 500MHz  
PROGRAMMABLE LVPECL AND HSTL  
BUS CLOCK SYNTHESIZER  
Precision Edge™  
SY89536L  
FEATURES  
Integrated synthesizer plus fanout buffers, clock  
Precision Edge™  
dividers, and translator in a single 64-pin package  
Accepts any reference input between 14MHz to  
DESCRIPTION  
160MHz (single-ended or differential)  
33MHz to 500MHz output frequency range  
LVPECL and HSTL outputs  
The SY89536L programmable clock synthesizer is part  
of a 3.3V, high-frequency, precision PLL-based clock  
synthesizer family optimized for multi-frequency, large clock-  
tree applications. This device integrates the following blocks  
into a single monolithic IC:  
3.3V ±10% power supply  
Low jitter: <50ps cycle-to-cycle  
Low pin-to-pin skew: <50ps  
• PLL (Phase-Lock-Loop)-based synthesizer  
• Fanout buffer  
• Clock generator (divider)  
TTL/CMOS compatible control logic  
3 independently programmable output frequency  
banks:  
• Logic translation (LVPECL, HSTL)  
• 9 differential output pairs @BankB (HSTL)  
• 2 differential output pairs @BankA (LVPECL)  
• 2 differential output pairs @BankC (LVPECL)  
The SY89536L includes a flexible input design that  
accepts any reference input; single-ended LVTTL/CMOS,  
SSTL and differential LVPECL, LVDS, HSTL, and CML.  
This level of integration minimizes the additive jitter and  
part-to-part skew associated with the discrete alternative,  
resulting in superior system-level timing as well as reduced  
board space and power. For applications that must interface  
to a crystal oscillator, see the SY89531L.  
Available in 64-pin EPAD-TQFP  
Data sheets and support documentation can be found on  
Micrel’s web site at www.micrel.com.  
APPLICATIONS  
PRODUCT SELECTION GUIDE  
Servers  
Input  
Output  
Workstations  
Device  
Crystal Reference BankA  
BankB  
BankC  
Parallel processor-based systems  
Other high-performance computing  
Communications  
SY89531L*  
SY89532L*  
SY89533L*  
SY89534L*  
SY89535L*  
SY89536L  
X
X
X
LVPECL HSTL LVPECL  
LVPECL LVPECL LVPECL  
LVPECL LVDS LVPECL  
LVPECL LVPECL LVPECL  
LVPECL LVDS LVPECL  
LVPECL HSTL LVPECL  
X
X
X
*Refer to individual data sheet for details.  
Precision Edge is a trademark of Micrel, Inc.  
Rev.: A  
Amendment: /0  
1
Issue Date: June 2003  

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