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SY87701LZGTR PDF预览

SY87701LZGTR

更新时间: 2024-11-13 20:27:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP ATM异步传输模式电信光电二极管电信集成电路
页数 文件大小 规格书
14页 151K
描述
Clock Recovery Circuit, 1-Func, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28

SY87701LZGTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP28,.4针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.82应用程序:ATM;SDH;SONET
JESD-30 代码:R-PDSO-G28JESD-609代码:e4
长度:17.93 mm湿度敏感等级:2
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:ATM/SONET/SDH ICs
最大压摆率:0.23 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.52 mmBase Number Matches:1

SY87701LZGTR 数据手册

 浏览型号SY87701LZGTR的Datasheet PDF文件第2页浏览型号SY87701LZGTR的Datasheet PDF文件第3页浏览型号SY87701LZGTR的Datasheet PDF文件第4页浏览型号SY87701LZGTR的Datasheet PDF文件第5页浏览型号SY87701LZGTR的Datasheet PDF文件第6页浏览型号SY87701LZGTR的Datasheet PDF文件第7页 
3.3V 32-1250Mbps AnyRate®  
CLOCK AND DATA RECOVERY  
L  
SY87701L  
Use lower-power SY87701AL for new designs  
DESCRIPTION  
FEATURES  
Industrial temperature range (–40°C to +85°C)  
3.3V power supply  
The SY87701L is a complete Clock Recovery and Data  
Retiming integrated circuit for data rates from 32Mbps  
up to 1.25Gbps NRZ. The device is ideally suited for  
SONET/SDH/ATM and Fibre Channel applications and  
other high-speed data transmission systems.  
Clock recovery and data retiming is performed by  
synchronizing the on-chip VCO directly to the incoming  
data stream. The VCO center frequency is controlled by  
the reference clock frequency and the selected divide  
ratio. On-chip clock generation is performed through the  
use of a frequency multiplier PLL with a byte rate source  
as reference.  
Clock and data recovery from 32Mbps up to  
1.25Gbps NRZ data stream, clock generation from  
32Mbps to 1.25Gbps  
Complies with Bellcore, ITU/CCITT and ANSI  
specifications for applications such as OC-1, OC-3,  
OC-12, ATM, FDDI, Fibre Channel and Gigabit  
Ethernet as well as proprietary applications  
Two on-chip PLLs: one for clock generation and  
another for clock recovery  
The SY87701L also includes a link fault detection  
circuit.  
All support documentation can be found on Micrel’s web  
site at www.micrel.com.  
Selectable reference frequencies  
Differential PECL high-speed serial I/O  
Line receiver input: no external buffering needed  
Link fault indication  
100k ECL compatible I/O  
APPLICATIONS  
Available in 32-pin EPAD-TQFP and 28-pin SOIC  
packages (28-pin SOIC is available, but NOT  
recommended for new designs.)  
SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24  
Fibre Channel, Escon, SMPTE 259  
Gigabit Ethernet/Fast Ethernet  
Proprietary architecture up to 1.25Gbps  
BLOCK DIAGRAM  
PLLR P/N  
RDOUTP  
(PECL)  
RDINP  
(PECL)  
RDINN  
PHASE  
DETECTOR  
RDOUTN  
RCLKP  
(PECL)  
0
1
CHARGE  
PUMP  
VCO  
RCLKN  
PHASE/  
FREQUENCY  
DETECTOR  
LINK  
FAULT  
DETECTOR  
LFIN  
(TTL)  
CD  
(PECL)  
REFCLK  
(TTL)  
PHASE/  
FREQUENCY  
DETECTOR  
CHARGE  
PUMP  
VCO  
TCLKP  
(PECL)  
1
0
TCLKN  
V
V
V
CC  
DIVIDER  
BY 8, 10, 16, 20  
CCA  
CCO  
SY87701L  
GND  
DIVSEL 1/2  
(TTL)  
FREQSEL 1/2/3  
(TTL)  
PLLS P/N  
CLKSEL  
(TTL)  
AnyRate is a registered trademark of Micrel, Inc.  
Rev.: G  
Amendment:/0  
M9999-111506  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: Novembe2006  

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