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SY87701ALZI PDF预览

SY87701ALZI

更新时间: 2024-11-13 20:42:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP ATM异步传输模式电信光电二极管电信集成电路
页数 文件大小 规格书
15页 148K
描述
Clock Recovery Circuit, 1-Func, PDSO28, 0.300 INCH, SOIC-28

SY87701ALZI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP28,.4
针数:28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.9
应用程序:ATM;SDH;SONETJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:17.93 mm
湿度敏感等级:1功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.16 mA
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn75Pb25)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.52 mmBase Number Matches:1

SY87701ALZI 数据手册

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SY87701AL  
3.3V 28Mbps to 1.3Gbps  
AnyRate® Clock and Data Recovery  
DESCRIPTION  
FEATURES  
Industrial temperature range (–40°C to +85°C)  
3.3V power supply  
The SY87701AL is a complete Clock Recovery and  
Data Retiming integrated circuit for data rates from  
28Mbps up to 1.3Gbps NRZ. The device is ideally suited  
for SONET/SDH/ATM and Fibre Channel applications and  
other high-speed data transmission systems.  
Clock recovery and data retiming is performed by  
synchronizing the on-chip VCO directly to the incoming  
data stream. The VCO center frequency is controlled by  
the reference clock frequency and the selected divide  
ratio. On-chip clock generation is performed through the  
use of a frequency multiplier PLL with a byte rate source  
as reference.  
Clock and data recovery from 28Mbps up to 1.3Gbps  
NRZ data stream, clock generation from 28Mbps to  
1.3Gbps  
Complies with Bellcore, ITU/CCITT and ANSI  
specifications for applications such as OC-1, OC-3,  
OC-12, ATM, FDDI, Fibre Channel and Gigabit  
Ethernet as well as proprietary applications  
Two on-chip PLLs: one for clock generation and  
another for clock recovery  
The SY87701AL also includes a link fault detection  
circuit.  
All support documentation can be found on Micrel’s web  
site at: www.micrel.com.  
Selectable reference frequencies  
Differential PECL high-speed serial I/O  
Line receiver input: no external buffering needed  
Link fault indication  
100k ECL compatible I/O  
APPLICATIONS  
Lower power: fully compatible with Micrel's  
SY87701V, but with 30% less power  
SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24  
Fibre Channel, Escon, SMPTE 259  
Gigabit Ethernet/Fast Ethernet  
Available in 32-pin EPAD-TQFP and 28-pin SOIC  
packages (28-pin SOIC is available, but NOT  
recommended for new designs.)  
Proprietary architecture up to 1.3Gbps  
BLOCK DIAGRAM  
PLLR P/N  
RDOUTP  
(PECL)  
RDINP  
(PECL)  
RDINN  
PHASE  
DETECTOR  
RDOUTN  
RCLKP  
(PECL)  
0
CHARGE  
PUMP  
VCO  
1
RCLKN  
PHASE/  
FREQUENCY  
DETECTOR  
LINK  
FAULT  
DETECTOR  
LFIN  
(TTL)  
CD  
(PECL)  
REFCLK  
(TTL)  
PHASE/  
FREQUENCY  
DETECTOR  
CHARGE  
PUMP  
VCO  
TCLKP  
(PECL)  
1
0
TCLKN  
VCC  
DIVIDER  
BY 8, 10, 16, 20  
VCCA  
VCCO  
GND  
SY87701AL  
DIVSEL 1/2  
(TTL)  
FREQSEL 1/2/3  
(TTL)  
PLLS P/N  
CLKSEL  
(TTL)  
AnyRate is a registered trademark of Micrel, Inc.  
Rev.: G  
Amendment:/0  
M9999-082107  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: August 2007  

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