Datasheet > SY10E256_06

SY10E256_06

更新时间： 2024-09-28 04:50:11

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	63K
描述
3-BIT 4:1 MUX-LATCH

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数据手册

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SY10E256_06 数据手册

SY10E256

SY100E256

Micrel, Inc.

3-BIT 4:1

SY10E256

SY100E256

MUX-LATCH

DESCRIPTION

FEATURES

■ 950ps max. data to output

The SY10/100E256 offer three 4:1 multiplexers followed

by latches with differential outputs designed for use in new,

high-performance ECL systems. Separate Select controls

are provided for the leading 2:1 mux pairs (see block

diagram).

■ Extended 100E VEE range of –4.2V to –5.5V

■ 850ps max. latch enable to output

■ Separate select controls

■ Differential outputs

When the Latch Enable (LEN) is at a logic LOW, the latch

istransparentandoutputdataiscontrolledbythemultiplexer

select controls. A logic HIGH on LEN latches the outputs.

The Master Reset (MR) overrides all other controls to set

the Q outputs LOW.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E256

■ Available in 28-pin PLCC package

PIN NAMES

BLOCK DIAGRAM

Function

Parallel Data Inputs

First-stage Select Inputs

Second-stage Select Input

Latch Enable

D0x–D2x

SEL1A, SEL1B

SEL2

LEN

D1a

D1b

D1c

D1d

Master Reset

Q0, Q0–Q2, Q2

VCCO

Data Outputs

VCC to Output

D2a

D2b

D2c

D2d

SEL1A

SEL1B

SEL

LEN

Rev.: G

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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