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SY10E150JC PDF预览

SY10E150JC

更新时间: 2024-11-22 22:34:35
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路
页数 文件大小 规格书
4页 63K
描述
6-BIT D LATCH

SY10E150JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
风险等级:5.88系列:10E
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm逻辑集成电路类型:D LATCH
湿度敏感等级:1位数:6
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):62 mA
Prop。Delay @ Nom-Sup:0.55 ns传播延迟(tpd):0.7 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:LOW LEVEL
宽度:11.48 mmBase Number Matches:1

SY10E150JC 数据手册

 浏览型号SY10E150JC的Datasheet PDF文件第2页浏览型号SY10E150JC的Datasheet PDF文件第3页浏览型号SY10E150JC的Datasheet PDF文件第4页 
6-BIT D  
LATCH  
SY10E150  
SY100E150  
DESCRIPTION  
FEATURES  
700ps max. propagation delay  
Extended 100E VEE range of –4.2V to –5.5V  
Differential outputs  
The SY10/100E150 are 6-bit D latches with differential  
outputs designed for use in new, high- performance ECL  
systems. When both Latch Enables (LEN1, LEN2) are at a  
logic LOW, the latch is in the transparent mode and input  
data propagates through to the output. A logic HIGH on  
either LEN1 or LEN2 (or both) latches the input data. The  
Master Reset (MR) overrides all other signals to set the Q  
outputs to a logic LOW.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E150  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN CONFIGURATION  
D0  
D1  
D2  
D3  
D4  
D5  
Q
0
0
D
D
R
R
R
R
R
R
Q
24 23 22 21 20 19  
25  
Q
1
1
18  
17  
16  
15  
14  
13  
12  
26  
27  
28  
1
D
5
Q
4
D4  
Q
4
Q
D
3
V
CC  
PLCC  
TOP VIEW  
J28-1  
VEE  
Q
Q
Q
Q
3
3
2
2
Q
2
2
D
D
D
D
D2  
2
Q
D1  
3
D
0
4
Q
3
3
5
6
7
8
9
10 11  
Q
Q
4
4
Q
Q
5
5
Q
LEN  
1
2
LEN  
PIN NAMES  
MR  
Pin  
D0–D5  
LEN1, LEN2  
MR  
Function  
Data Inputs  
Latch Enables  
Master Reset  
True Outputs  
Q0–Q5  
Q0–Q5  
VCCO  
Inverting Outputs  
VCC to Output  
Rev.: D  
Amendment: /0  
Issue Date: November, 1998  
1

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