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SY10E151 PDF预览

SY10E151

更新时间: 2024-01-11 04:35:26
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 64K
描述
6-BIT D REGISTER

SY10E151 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.66
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:2
位数:6功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245传播延迟(tpd):0.8 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:1100 MHzBase Number Matches:1

SY10E151 数据手册

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6-BIT D  
REGISTER  
SY10E151  
SY100E151  
FEATURES  
DESCRIPTION  
1100MHz toggle frequency  
Extended 100E VEE range of –4.2V to –5.46V  
Differential outputs  
The SY10/100E151 offer 6 edge-triggered, high-speed,  
master-slave D-type flip-flops with differential outputs,  
designed for use in new, high-performance ECL systems.  
The two external clock signals (CLK1, CLK2) are gated  
through a logical OR operation before use as clocking  
control for the flip-flops. Data is clocked into the flip-flops  
on the rising edge of either CLK1 or CLK2 (or both). When  
both CLK1 and CLK2 are at a logic LOW, data enters the  
master and is transferred to the slave when either CLK1 or  
CLK2 (or both) go HIGH.  
Asynchronous Master Reset  
Dual clocks  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E151  
Available in 28-pin PLCC package  
The MR (Master Reset) signal operates asynchronously  
to make all Q outputs go to a logic LOW.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
D0  
D1  
D2  
D3  
D4  
D5  
Q
0
0
D
D
Q
R
R
R
R
R
R
24 23 22 21 20 19  
25  
Q
1
1
26  
27  
28  
18  
17  
16  
15  
14  
13  
12  
D
5
Q
4
D4  
Q
4
Q
D
3
V
CC  
PLCC  
TOP VIEW  
J28-1  
VEE  
Q
Q
Q
Q
3
3
2
2
1
2
3
4
Q
2
2
D
D
D
D
D2  
Q
D1  
D
0
Q
3
3
5
6
7
8
9
10 11  
Q
Q
4
4
Q
Q
5
5
PIN NAMES  
Q
CLK  
CLK  
1
2
Pin  
D0–D5  
CLK1, CLK2  
MR  
Function  
Data Inputs  
Clock Inputs  
Master Reset  
True Outputs  
M
R
Q0–Q5  
Q0–Q5  
VCCO  
Inverting Outputs  
VCC to Output  
Rev.: D  
Amendment: /0  
Issue Date: November, 1998  
1

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