Datasheet > SY10E154_06

SY10E154_06

更新时间： 2024-09-29 05:04:27

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	63K
描述
5-BIT 2:1 MUX-LATCH

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数据手册

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SY10E154_06 数据手册

SY10E154

SY100E154

Micrel, Inc.

5-BIT 2:1

MUX-LATCH

SY10E154

SY100E154

FEATURES

DESCRIPTION

■ 750ps max. LEN to output

■ Extended 100E VEE range of –4.2V to –5.5V

■ 700ps max. D to output

The SY10/100E154 offer five 2:1 multiplexers followed

by latches with differential outputs, designed for use in

new, high-performance ECL systems. The two external

Latch-Enable signals (LEN1, LEN2) are gated through a

logical OR operation before use as control for the five

latches. When both LEN1 and LEN2 are at a logic LOW, the

latches are transparent, thus presenting the data from the

multiplexers at the output pins. If either LEN1 or LEN2 (or

both) are at a logic HIGH, the outputs are latched.

ThemultiplexeroperationiscontrolledbytheSEL(Select)

signal which selects one of the two bits of input data at each

mux to be passed through.

■ Differential outputs

■ Asynchronous Master Reset

■ Dual latch-enables

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E154

■ Available in 28-pin PLCC package

The MR (Master Reset) signal operates asynchronously

to make all Q outputs go to a logic LOW.

BLOCK DIAGRAM

PIN NAMES

D0a–D4a

D0b–D4b

SEL

Function

Input Data a

D0a

D0b

D1a

D1b

D2a

D2b

D3a

D3b

D4a

D4b

MUX

SEL

Input Data b

Data Select Input

Latch Enables

Master Reset

True Outputs

Inverted Outputs

VCC to Output

LEN1, LEN2

MUX

SEL

Q0–Q4

VCCO

MUX

SEL

MUX

SEL

MUX

SEL

LEN1

LEN2

Rev.: E

Amendment: /0

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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