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SY10E151JITR PDF预览

SY10E151JITR

更新时间: 2024-09-29 21:13:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路触发器
页数 文件大小 规格书
4页 60K
描述
D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28

SY10E151JITR 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
系列:10EJESD-30 代码:S-PQCC-J28
长度:11.48 mm逻辑集成电路类型:D FLIP-FLOP
位数:6功能数量:1
端子数量:28输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):0.8 ns座面最大高度:4.57 mm
表面贴装:YES技术:ECL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:1100 MHz
Base Number Matches:1

SY10E151JITR 数据手册

 浏览型号SY10E151JITR的Datasheet PDF文件第2页浏览型号SY10E151JITR的Datasheet PDF文件第3页浏览型号SY10E151JITR的Datasheet PDF文件第4页 
1  
1  
6-BIT D  
SY10E151  
SY100E151  
REGISTER  
DESCRIPTION  
FEATURES  
1100MHz toggle frequency  
Extended 100E VEE range of –4.2V to –5.46V  
Differential outputs  
The SY10/100E151 offer 6 edge-triggered, high-speed,  
master-slave D-type flip-flops with differential outputs,  
designed for use in new, high-performance ECL systems.  
The two external clock signals (CLK1, CLK2) are gated  
through a logical OR operation before use as clocking  
control for the flip-flops. Data is clocked into the flip-flops  
on the rising edge of either CLK1 or CLK2 (or both). When  
both CLK1 and CLK2 are at a logic LOW, data enters the  
master and is transferred to the slave when either CLK1 or  
CLK2 (or both) go HIGH.  
Asynchronous Master Reset  
Dual clocks  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E151  
Available in 28-pin PLCC package  
The MR (Master Reset) signal operates asynchronously  
to make all Q outputs go to a logic LOW.  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
D0–D5  
CLK1, CLK2  
MR  
Function  
Data Inputs  
D0  
D1  
D2  
D3  
D4  
D5  
Q
0
0
D
D
Q
R
R
R
R
R
R
Clock Inputs  
Master Reset  
True Outputs  
Inverting Outputs  
VCC to Output  
Q
1
1
Q0–Q5  
Q0–Q5  
VCCO  
Q
Q
2
2
D
D
D
D
Q
Q
3
3
Q
Q
4
4
Q
Q
5
5
Q
CLK  
CLK  
1
2
M
R
Rev.: H  
Amendment: /0  
M9999-052108  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: May 2008  

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