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SY100S370FC PDF预览

SY100S370FC

更新时间: 2024-11-03 22:59:23
品牌 Logo 应用领域
麦瑞 - MICREL 解码器驱动器逻辑集成电路
页数 文件大小 规格书
7页 115K
描述
UNIVERSAL DEMULTIPLEXER/ DECODER

SY100S370FC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFF, QFL24,.4SQ
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.75Is Samacsys:N
其他特性:USABLE AS 1-OF-8 DECODER系列:100S
JESD-30 代码:S-GQFP-F24JESD-609代码:e0
长度:9.78 mm逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:2端子数量:24
最高工作温度:85 °C最低工作温度:
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:QFF封装等效代码:QFL24,.4SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):240电源:-4.5 V
最大电源电流(ICC):92 mAProp。Delay @ Nom-Sup:1.6 ns
传播延迟(tpd):1.6 ns认证状态:Not Qualified
座面最大高度:2.29 mm子类别:Decoder/Drivers
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:9.78 mmBase Number Matches:1

SY100S370FC 数据手册

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UNIVERSAL  
SY100S370  
DEMULTIPLEXER/  
DECODER  
FEATURES  
DESCRIPTION  
Max. propagation delay of 1200ps  
IEE min. of –92mA  
The SY100S370 is a universal demultiplexer/decoder  
that can be used as either a dual 1-of-4 decoder or as a  
single 1-of-8 decoder and is designed for use in high-  
performance ECL systems. The Mode control (M) input  
determines the function. In the dual 1-of-4 mode, each 4-  
input group has a pair of active-LOW Enable (E) inputs.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved The Enable pins are assigned such that in the single 1-of-  
noise immunity  
8 mode they can be tied together in pairs to result in two  
active-LOW Enable inputs. E1a will be tied to E1b and E2a  
to E2b.  
The auxiliary inputs (Hn) are used to determine whether  
the outputs are active-HIGH or active-LOW. The address  
Internal 75Kinput pull-down resistors  
60% faster than National or Signetics  
Approximately 40% lower power than Fairchild  
Function and pinout compatible with Fairchild F100K inputs for the dual 1-of-4 mode are A0a, A1a, A0b. A2a is  
unused. In the 1-of-8 mode, the address inputs are A0a,  
A1a, A2a. The inputs on the device have 75Kpull-down  
resistors.  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
PIN CONFIGURATIONS  
PIN NAMES  
11 10 9  
8 7 6 5  
Pin  
Ana, Anb  
Ena, Enb  
M
Function  
E
1a  
1b  
12  
13  
14  
15  
16  
17  
18  
4
3
Z
Z
0a (Z  
0
)
)
E
3a (Z  
3
Address Inputs (n = 0,1,2)  
Enable Inputs (n = 1,2)  
V
EE  
EES  
2b  
2a  
2
V
V
V
CCA  
Top View  
PLCC  
V
1
CC  
J28-1  
E
28  
27  
26  
CC  
Mode Control Input  
Z
Z
1b (Z  
5
)
)
E
Ha  
Z0 – Z3 (Z0a – Z3a) Polarity Select Input  
Z4 – Z7 (Z0b – Z3b) Polarity Select Input  
Common Polarity Select Input  
Single 1-of-8 Data Outputs  
Dual 1-of-4 Data Outputs (n = 1...4)  
VEE Substrate  
2b (Z  
6
H
a
19 20 21 22 23 24 25  
Hb  
Hc  
Z0 – Z7  
Zna, Znb  
VEES  
VCCA  
24 23 22 21 20 19  
18  
VCCO for ECL Outputs  
1
2
3
4
5
6
H
c
A2a  
H
b
17  
16  
15  
14  
13  
M
Top View  
Flatpack  
F24-1  
A
0b  
1b  
A
1a  
0a  
1a (Z  
2a (Z  
A
A
Z
3b (Z  
7
)
Z
Z
1
)
)
Z
0b (Z  
4
)
2
7
8
9 10 11 12  
Rev.: G  
Amendment:/0  
1
Issue Date: July, 1999  

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