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STK12C68-WF45 PDF预览

STK12C68-WF45

更新时间: 2024-11-10 20:18:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
22页 1854K
描述
Non-Volatile SRAM, 8KX8, 45ns, CMOS, PDIP28, 0.600 INCH, ROHS COMPLIANT, PLASTIC, MS-011, DIP-28

STK12C68-WF45 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.600 INCH, ROHS COMPLIANT, PLASTIC, MS-011, DIP-28针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:5.19最长访问时间:45 ns
JESD-30 代码:R-PDIP-T28JESD-609代码:e4
长度:36.32 mm内存密度:65536 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:5.08 mm最大待机电流:0.0015 A
子类别:SRAMs最大压摆率:0.065 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:15.24 mm
Base Number Matches:1

STK12C68-WF45 数据手册

 浏览型号STK12C68-WF45的Datasheet PDF文件第2页浏览型号STK12C68-WF45的Datasheet PDF文件第3页浏览型号STK12C68-WF45的Datasheet PDF文件第4页浏览型号STK12C68-WF45的Datasheet PDF文件第5页浏览型号STK12C68-WF45的Datasheet PDF文件第6页浏览型号STK12C68-WF45的Datasheet PDF文件第7页 
STK12C68  
64 Kbit (8 K x 8) AutoStore nvSRAM  
Features  
Functional Description  
25 ns, 35 ns, and 45 ns access times  
The Cypress STK12C68 is a fast static RAM with a nonvolatile  
element in each memory cell. The embedded nonvolatile  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
Hands off automatic STORE on power-down with external  
68 µF capacitor  
unlimited read and write cycles, while independent nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power-down. On  
power-up, data is restored to the SRAM (the RECALL operation)  
from the nonvolatile memory. Both the STORE and RECALL  
operations are also available under software control. A hardware  
STORE is initiated with the HSB pin.  
STORE to QuantumTrap nonvolatile elements is initiated by  
software, hardware, or AutoStore on power-down  
RECALL to SRAM initiated by software or power-up  
Unlimited read, write, and recall cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5 V + 10% operation  
For a complete list of related documentation, click here.  
Commercial and industrial temperatures  
28-pin (330 mil) SOIC, 28-pin (300 mil) PDIP, 28-pin (600 mil)  
PDIP packages  
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages  
RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
128 X 512  
A5  
A6  
POWER  
CONTROL  
STORE  
A7  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
128 X 512  
A8  
HSB  
A9  
A11  
A12  
SOFTWARE  
DETECT  
A0  
-
A12  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-51027 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 17, 2014  

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