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STK12C68-W20 PDF预览

STK12C68-W20

更新时间: 2024-11-07 23:11:03
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其他 - ETC 存储内存集成电路静态存储器光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 126K
描述
8k x 8 AUTOSTORE NVSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM

STK12C68-W20 数据手册

 浏览型号STK12C68-W20的Datasheet PDF文件第2页浏览型号STK12C68-W20的Datasheet PDF文件第3页浏览型号STK12C68-W20的Datasheet PDF文件第4页浏览型号STK12C68-W20的Datasheet PDF文件第5页浏览型号STK12C68-W20的Datasheet PDF文件第6页浏览型号STK12C68-W20的Datasheet PDF文件第7页 
STK12C68  
8K x 8 AutoStore™ nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
20ns, 25ns, 35ns and 45ns Access Times  
The Simtek STK12C68 is a fast static RAM with a  
• “Hands-offAutomatic STORE with External  
68µF Capacitor on Power Down  
nonvolatile, electrically erasable PROM element  
incorporated in each static memory cell. The SRAM  
can be read and written an unlimited number of  
times, while independent, nonvolatile data resides in  
EEPROM. Data transfers from the SRAM to the  
EEPROM (the STORE operation) can take place  
automatically on power down. A 68µF or larger  
capacitor tied from VCAP to ground guarantees the  
STORE operation, regardless of power-down slew  
rate or loss of power from “hot swapping”. Transfers  
from the EEPROM to the SRAM (the RECALL opera-  
tion) take place automatically on restoration of  
power. Initiation of STORE and RECALL cycles can  
also be software controlled by entering specific read  
sequences. A hardware STORE may be initiated with  
the HSB pin.  
STORE to EEPROM Initiated by Hardware,  
Software or AutoStoreon Power Down  
RECALL to SRAM Initiated by Software or  
Power Restore  
10mA Typical ICC at 200ns Cycle Time  
Unlimited READ, WRITE and RECALL Cycles  
1,000,000 STORE Cycles to EEPROM  
100-Year Data Retention in EEPROM  
Single 5V + 10% Operation  
Not Sensitive to Power On/Off Ramp Rates  
No Data Loss from Undershoot  
Commercial and Industrial Temperatures  
28-Pin SOIC and DIP Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
VCCX  
VCAP  
V
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
V
CCX  
CAP  
A
2
W
HSB  
12  
3
A
7
6
5
4
3
2
A
4
A
POWER  
CONTROL  
8
EEPROM ARRAY  
128 x 512  
A
A
A
A
9
A
11  
G
5
6
A5  
A6  
7
A
8
A
E
10  
STORE  
STORE/  
RECALL  
CONTROL  
A
9
1
HSB  
A7  
A
DQ  
0
DQ  
10  
11  
12  
13  
14  
19  
18  
17  
16  
15  
DQ  
DQ  
DQ  
DQ  
DQ  
0
7
6
STATIC RAM  
28 - 300 PDIP  
28 - 600 PDIP  
28 - 350 SOIC  
28 - 300 CDIP  
RECALL  
A8  
ARRAY  
1
2
5
128 x 512  
A9  
DQ  
V
4
3
A11  
A12  
SS  
SOFTWARE  
DETECT  
A0 - A12  
PIN NAMES  
DQ0  
DQ1  
DQ2  
COLUMN I/O  
A - A  
Address Inputs  
0
12  
COLUMN DEC  
DQ -DQ  
0
Data In/Out  
7
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
E
Chip Enable  
W
Write Enable  
Output Enable  
Hardware Store Busy (I/O)  
Power (+ 5V)  
Capacitor  
A0 A1 A2 A3 A4 A10  
G
G
HSB  
E
V
V
V
CCX  
CAP  
SS  
W
Ground  
July 1999  
4-41  

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