Datasheet > STK12C68-5C25

STK12C68-5C25

更新时间： 2024-02-02 12:57:28

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
13页	371K
描述
8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM

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技术参数
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STK12C68-5C25 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP28,.3	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.2.C	HTS代码：	8542.32.00.41
风险等级：	5.21	Is Samacsys：	N
最长访问时间：	25 ns	JESD-30 代码：	R-CDIP-T28
JESD-609代码：	e0	长度：	35.56 mm
内存密度：	65536 bit	内存集成电路类型：	NON-VOLATILE SRAM
内存宽度：	8	功能数量：	1
端子数量：	28	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	8KX8	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装等效代码：	DIP28,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
筛选级别：	38535Q/M;38534H;883B	座面最大高度：	4.14 mm
最大待机电流：	0.0025 A	子类别：	SRAMs
最大压摆率：	0.09 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

STK12C68-5C25 数据手册

STK12C68

DEVICE OPERATION

The STK12C68 has two separate modes of opera-

tion: SRAM mode and nonvolatile mode. In SRAM

mode, the memory operates as a standard fast

static RAM. In nonvolatile mode, data is transferred

from SRAM to Nonvolatile Elements (the STORE

operation) or from Nonvolatile Elements to SRAM

(the RECALL operation). In this mode SRAM func-

tions are disabled.

POWER-UP RECALL

During power up, or after any low-power condition

(V_CAP< V_RESET), an internal RECALL request will be

latched. When V_CAPonce again exceeds the sense

voltage of V_SWITCH, a RECALL cycle will automatically

be initiated and will take t_RESTOREto complete.

If the STK12C68 is in a WRITE state at the end of

power-up RECALL, the SRAM data will be corrupted.

To help avoid this situation, a 10K Ohm resistor

should be connected either between W and system

V_CCor between E and system V_CC.

NOISE CONSIDERATIONS

The STK12C68 is a high-speed memory and so

must have a high-frequency bypass capacitor of

approximately 0.1µF connected between V_CAPand

V_SS, using leads and traces that are as short as pos-

sible. As with all high-speed CMOS ICs, normal care-

ful routing of power, ground and signals will help

prevent noise problems.

SOFTWARE NONVOLATILE STORE

The STK12C68 software STORE cycle is initiated by

executing sequential E controlled READ cycles from

six specific address locations. During the STORE

cycle an erase of the previous nonvolatile data is

first performed, followed by a program of the nonvol-

atile elements. The program operation copies the

SRAM data into nonvolatile memory. Once a STORE

cycle is initiated, further input and output are dis-

abled until the cycle is completed.

SRAM READ

The STK12C68 performs a READ cycle whenever E

and G are low and W and HSB are high. The

address specified on pins A_0-12determines which of

the 8,192 data bytes will be accessed. When the

READ is initiated by an address transition, the out-

puts will be valid after a delay of t_AVQV(READ cycle

#1). If the READ is initiated by E or G, the outputs will

be valid at t_ELQVor at t_GLQV, whichever is later (READ

cycle #2). The data outputs will repeatedly respond

to address changes within the t_AVQVaccess time with-

out the need for transitions on any control input pins,

and will remain valid until another address change or

until E or G is brought high, or W or HSB is brought

low.

Because a sequence of READs from specific

addresses is used for STORE initiation, it is impor-

tant that no other READ or WRITE accesses inter-

vene in the sequence, or the sequence will be

aborted and no STORE or RECALL will take place.

To initiate the software STORE cycle, the following

READ sequence must be performed:

1. Read address

2. Read address

3. Read address

4. Read address

5. Read address

6. Read address

0000 (hex)

1555 (hex)

0AAA (hex)

1FFF (hex)

10F0 (hex)

0F0F (hex)

Valid READ

SRAM WRITE

Valid READ

A WRITE cycle is performed whenever E and W are

low and HSB is high. The address inputs must be

stable prior to entering the WRITE cycle and must

remain stable until either E or W goes high at the

end of the cycle. The data on the common I/O pins

DQ_0-7will be written into the memory if it is valid t_DVWH

before the end of a W controlled WRITE or t_DVEH

before the end of an E controlled WRITE.

Initiate STORE cycle

The software sequence must be clocked with E con-

trolled READs.

Once the sixth address in the sequence has been

entered, the STORE cycle will commence and the

chip will be disabled. It is important that READ cycles

and not WRITE cycles be used in the sequence,

although it is not necessary that G be low for the

sequence to be valid. After the t_STOREcycle time has

been fulfilled, the SRAM will again be activated for

READ and WRITE operation.

It is recommended that G be kept high during the

entire WRITE cycle to avoid data bus contention on

common I/O lines. If G is left low, internal circuitry

will turn off the output buffers t_WLQZafter W goes low.

October 2003

Document Control # ML0008 rev 0.4

1...5 6 789 10 11...13

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与STK12C68-5C25相关器件

型号	品牌	描述	获取价格	数据表
STK12C68-5C25I	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C25M	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C30	CYPRESS	8KX8 NON-VOLATILE SRAM, 30ns, CDIP28, 0.300 INCH, CERAMIC, DIP-28	获取价格
STK12C68-5C30I	ETC	NVRAM (EEPROM Based)	获取价格
STK12C68-5C35	CYPRESS	8KX8 NON-VOLATILE SRAM, 35ns, CDIP28, 0.300 INCH, CERAMIC, DIP-28	获取价格
STK12C68-5C35I	CYPRESS	8KX8 NON-VOLATILE SRAM, 35ns, CDIP28, 0.300 INCH, CERAMIC, DIP-28	获取价格

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