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STH6N100 PDF预览

STH6N100

更新时间: 2024-11-08 22:21:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 晶体晶体管
页数 文件大小 规格书
10页 204K
描述
N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR

STH6N100 数据手册

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STH6N100  
STH6N100FI  
N - CHANNEL ENHANCEMENT MODE  
POWER MOS TRANSISTOR  
TYPE  
VDSS  
RDS(on)  
ID  
STH6N100  
STH6N100FI  
1000 V  
1000 V  
< 2 Ω  
< 2 Ω  
6 A  
3.7 A  
TYPICAL RDS(on) = 1.75 Ω  
AVALANCHE RUGGED TECHNOLOGY  
100% AVALANCHE TESTED  
REPETITIVE AVALANCHE DATA AT 100oC  
LOW INPUT CAPACITANCE  
LOW GATE CHARGE  
3
3
2
2
1
1
APPLICATION ORIENTED  
CHARACTERIZATION  
TO-218  
ISOWATT218  
APPLICATIONS  
HIGH CURRENT, HIGH SPEED SWITCHING  
SWITCH MODE POWER SUPPLIES (SMPS)  
CONSUMER AND INDUSTRIAL LIGHTING  
DC-AC INVERTERS FOR WELDING  
EQUIPMENT AND UNINTERRUPTIBLE  
POWER SUPPLY (UPS)  
INTERNAL SCHEMATIC DIAGRAM  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
STH6N100  
STH6N100  
VDS  
VDG R  
VGS  
ID  
Drain-source Voltage (VGS = 0)  
Drain- gate Voltage (RGS = 20 k)  
Gate-source Voltage  
Drain Current (continuous) at Tc = 25 oC  
Drain Current (continuous) at Tc = 100 oC  
Drain Current (pulsed)  
1000  
1000  
± 20  
V
V
V
6
3.7  
2.3  
A
ID  
3.7  
24  
A
IDM()  
Ptot  
24  
A
Total Dissipation at Tc = 25 oC  
180  
1.44  
70  
W
W/oC  
V
oC  
oC  
Derating Factor  
0.56  
4000  
VISO  
Tstg  
Tj  
Insulation Withstand Voltage (DC)  
Storage Temperature  
-65 to 150  
150  
Max. Operating Junction Temperature  
() Pulse width limited by safe operating area  
1/10  
December 1996  

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