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SPC5646BF0VLU1 PDF预览

SPC5646BF0VLU1

更新时间: 2024-10-29 15:17:51
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
116页 1552K
描述
NXP 32-bit MCU, Power Arch core, 3MB Flash, 80MHz, -40/+105degC, Automotive Grade, QFP 176

SPC5646BF0VLU1 数据手册

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NXP Semiconductors  
Data Sheet: Technical Data  
Document Number: MPC5646C  
Rev. 7, 11/2021  
MPC5646C  
176-pin LQFP  
208-pin LQFP  
(24 mm x 24 mm)  
(28 mm x 28 mm)  
MPC5646C Microcontroller  
Datasheet  
256 MAPBGA  
(17 mm x 17 mm)  
Real Time Counter (RTC) with clock source from internal 128  
kHz or 16 MHz oscillators or external 4–40 MHz crystal  
On-chip modules available within the family include the following  
features:  
Supports autonomous wake-up with 1 ms resolution with  
max timeout of 2 seconds  
Optional support from external 32 kHz crystal oscillator,  
supporting wake-up with 1 second resolution and max  
timeout of 1 hour  
e200z4d dual issue, 32-bit core Power Architecture  
compliant CPU  
Up to 120 MHz  
4 KB, 2/4-Way Set Associative Instruction Cache  
Variable length encoding (VLE)  
Embedded floating-point (FPU) unit  
Supports Nexus3+  
1 System Timer Module (STM) with four 32-bit compare  
channels  
Up to 8 periodic interrupt timers (PIT) with 32-bit counter  
resolution  
1 Real Time Interrupt (RTI) with 32-bit counter resolution  
1 Safety Enhanced Software Watchdog Timer (SWT) that  
supports keyed functionality  
1 dual-channel FlexRay Controller with 128 message buffers  
1 Fast Ethernet Controller (FEC)  
On-chip voltage regulator (VREG)  
Cryptographic Services Engine (CSE)  
Offered in the following standard package types:  
176-pin LQFP, 24 × 24 mm, 0.5 mm Lead Pitch  
208-pin LQFP, 28 × 28 mm, 0.5 mm Lead Pitch  
256-ball MAPBGA, 17 × 17mm, 1.0 mm Lead Pitch  
e200z0h single issue, 32-bit core Power Architecture compliant  
CPU  
Up to 80 MHz  
Variable length encoding (VLE)  
Supports Nexus3+  
Up to 3 MB on-chip flash memory: flash page buffers to improve  
access time  
Up to 256 KB on-chip SRAM  
64 KB on-chip data flash memory to support EEPROM emulation  
Up to 16 semaphores across all slave ports  
User selectable MBIST  
Low-power modes supported: STOP, HALT, STANDBY  
16 region Memory Protection Unit (MPU)  
Dual-core Interrupt Controller (INTC). Interrupt sources can be  
routed to e200z4d, e200z0h, or both  
Crossbar switch architecture for concurrent access to peripherals,  
flash memory, and SRAM from multiple bus masters  
32 channel eDMA controller with DMAMUX  
Timer supports input/output channels providing 16-bit input  
capture, output compare, and PWM functions (eMIOS)  
2 analog-to-digital converters (ADC): one 10-bit and one 12-bit  
Cross Trigger Unit (CTU) to enable synchronization of ADC  
conversions with a timer event from the eMIOS or from the PIT  
Up to 8 serial peripheral interface (DSPI) modules  
Up to 10 serial communication interface (LINFlex) modules  
Up to 6 full CAN (FlexCAN) modules with 64 MBs each  
CAN Sampler to catch ID of CAN message  
1 inter IC communication interface (I2C) module  
Up to 177 (LQFP) or 199 (BGA) configurable general purpose I/O  
pins  
System clocks sources  
4–40 MHz external crystal oscillator  
16 MHz internal RC oscillator  
FMPLL  
Additionally, there are two low power oscillators: 128 kHz  
internal RC oscillator, 32 kHz external crystal oscillator  
NXP reserves the right to change the proudction detail specifications as may be  
required to permit improvements in the design of its products  

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