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SP5769AKGQP1S

更新时间: 2024-11-28 22:05:35
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MITEL /
页数 文件大小 规格书
11页 226K
描述
3GHz I2C Bus Synthesiser

SP5769AKGQP1S 数据手册

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SP5769  
3GHz I2C Bus Synthesiser  
Preliminary information  
DS4878 Issue 4.0 October 1999  
Features  
Ordering Information  
G Complete 3·0 GHz Single Chip System  
G Optimised for Low Phase Noise, with Comparison  
Frequencies up to 4 MHz  
SP5769A/KG/MP1S (Tubes)  
SP5769A/KG/MP1T (Tape and Reel)  
SP5769A/KG/QP1S (Tubes)  
G No RF Prescaler  
SP5769A/KG/QP1T (Tape and Reel)  
G Selectable Reference Division Ratio  
G Selectable Reference/Comparison Frequency Output  
G Selectable Charge Pump Current with 10:1 Ratio  
G Four Selectable I2C Addresses  
size equal to the loop comparison frequency and no  
prescaler phase noise degradation over the full RF  
operating range. The comparison frequency is obtained  
either from an on-chip crystal controlled oscillator, or from  
an external source. The oscillator frequency, fREF, or phase  
comparator frequency, fCOMP, can be switched to the REF/  
COMP output providing a reference for a second frequency  
synthesiser. The synthesiser is controlled via an 12C bus  
G I2C Fast Mode Compliant with 3·3V and 5V Logic Levels  
G Four Switching Ports  
G Functional Replacement for SP5659 (except ADC)  
G Pin Compatible with SP5655  
G Power Consumption 110mW with VCC = 5·5V, all Ports off  
G ESD Protection 2kV min., MIL-STD-883B Method 3015  
Cat.1 (Normal ESD handling procedures should be  
observed)  
Absolute Maximum Ratings  
All voltages are referred to VEE = 0V  
Supply voltage, VCC  
0·3V to 17V  
2·5Vp-p  
20·3 to VCC 10·3V  
20·3 to 6V  
Applications  
RF differential input voltage  
All I/O port DC offsets  
SDA and SCL DC offset  
Storage temperature  
Junction temperature  
MP16 thermal resistance  
Chip to ambient, θJA  
Chip to case, θJC  
G Digital Satellite and Cable Tuning Systems  
G Communications Systems  
255°C to 1125°C  
The SP5769 is a single chip frequency synthesiser  
designed for tuning systems up to 3GHz. The RF  
preamplifier interfaces direct with the RF programmable  
divider, which is of MN1A construction so giving a step  
1150°C  
80°C/W  
20°C/W  
11  
REF/COMP  
2
ENABLE/  
SELECT  
CRYSTAL CAP  
11-BIT  
COUNT  
REFERENCE  
DIVIDER  
13  
RF  
INPUT  
416/17  
3
14  
CRYSTAL  
4-BIT  
COUNT  
1
CHARGE PUMP  
LOCK  
/2  
16  
DRIVE  
PUMP  
f
PD  
CP TEST  
MODE SET  
2 BIT  
4 BIT  
2 BIT  
3 BIT  
15-BIT LATCH  
10  
4
ADDRESS  
SDA  
2
I C BUS  
TRANSCEIVER  
5
SCL  
f /2 SELECT  
PD  
4-BIT LATCH AND  
PORT INTERFACE  
6
7
8
9
P3 P2  
P1 P0  
Figure 1 SP5769 block diagram  

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