SP5848KG PDF预览

SP5848KG

更新时间: 2025-07-13 22:42:51
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
9页 70K
描述
2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL

SP5848KG 数据手册

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Preiminary Information  
SP5848  
2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL  
Preliminary Information  
DS5076  
Issue 1.6  
October 1999  
Features  
Ordering Information  
G Dual independent PLL frequency synthesisers in a  
single package, optimised for double conversion  
cable tuners, offering improved application  
SP5848/KG/QP1S  
SP5848/KG/QP1T  
G 2.2GHz up-synthesiser optimised for low phase  
noise up to comparison frequencies of 4MHz  
Description  
G 1.3GHz down-synthesiser optimised for low phase  
noise AND small step size  
The SP5848 is a dual PLL frequency synthesizer  
controlled by a 3-wire bus optimised for application in  
double conversion tuners.  
G Common reference oscillator and divider with  
independently selectable ratios for each  
synthesiser  
G 10:1 programmable charge pump current ratio in up  
synthesiser  
G 3-Wire bus programmable, each synthesiser  
Each synthesiser loop within the SP5848 is  
independently addressable and contains an RF  
programmable divider, phase/frequency detector and  
charge pump/loop amplifier section; a common  
reference frequency oscillator and divider chain is  
provided, whose ratios for each loop are independently  
programmable.  
indepently addressable  
G Low power consumption, typ 100mW at 5V  
G ESD protection, (Normal ESD handling procedures  
should be observed)  
Both synthesisers are optimised for low phase noise  
performance and in addition synthesiser 2 is capable of  
operation with a low comparison frequency.  
Applications  
G TV, VCR, and cable tuning systems  
PUMP 1  
DRIVE 1  
11 BIT  
COUNT  
RF1 INPUT  
16/17  
4 BIT  
COUNT  
PORT P0  
15 BIT LATCH  
2 BIT  
LATCH  
2 BIT  
LATCH  
PORT P1  
DATA  
DATA  
INTERFACE  
CLOCK  
5 BIT  
LATCH  
29  
DIVIDE  
ENABLE  
1 BIT  
LATCH  
16 BIT LATCH  
PUMP 2  
DRIVE 2  
12 BIT  
COUNT  
16/17  
4 BIT  
RF 2 INPUT  
COUNT  
Figure 1 Block Diagram  

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