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SNJ54ALS323J PDF预览

SNJ54ALS323J

更新时间: 2024-11-21 01:13:03
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
13页 391K
描述
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

SNJ54ALS323J 数据手册

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ꢋ ꢌꢍꢎ ꢏꢉ ꢐꢁꢎ ꢑꢒꢓ ꢀꢄꢅꢉꢀ ꢔꢎꢕ ꢏ ꢖꢀ ꢏꢗ ꢓꢄꢘ ꢒꢉ ꢓꢒꢘ ꢎ ꢀꢏ ꢒꢓ  
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994  
SN54ALS323 . . . J PACKAGE  
SN74ALS323 . . . DW OR N PACKAGE  
(TOP VIEW)  
Multiplexed I/O Ports Provide Improved Bit  
Density  
Four Modes of Operation:  
− Hold (Store)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
S0  
OE1  
OE2  
V
CC  
− Shift Right  
− Shift Left  
− Load Data  
S1  
SL  
Q
G/Q  
G
H  
Operate With Outputs Enabled or at High  
E/Q  
H/Q  
E
H
Impedance  
C/Q  
F/Q  
C
F
3-State Outputs Drive Bus Lines Directly  
Can Be Cascaded for n-Bit Word Lengths  
Synchronous Clear  
A/Q  
Q
D/Q  
B/Q  
A
D
A′  
B
CLR  
GND  
CLK  
SR  
Applications:  
− Stacked or Push-Down Registers  
− Buffer Storage  
SN54ALS323 . . . FK PACKAGE  
(TOP VIEW)  
− Accumulator Registers  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) 300-mil DIPs  
3
2
1
20 19  
18  
4
5
6
7
8
G/Q  
SL  
Q
G
17  
16  
15  
14  
E/Q  
E
H′  
description  
C/Q  
H/Q  
C
H
F
A/Q  
Q
F/Q  
A
These 8-bit universal shift/storage registers  
feature multiplexed input/output (I/O) ports to  
achieve full 8-bit data handling in a 20-pin  
package. Two function-select (S0, S1) inputs and  
two output-enable (OE1, OE2) inputs can be used  
to choose the modes of operation listed in the  
function table.  
D/Q  
A′  
D
9 10 11 12 13  
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs  
in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading  
out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs  
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has  
no effect on clearing, shifting, or storing data.  
The SN54ALS323 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74ALS323 is characterized for operation from 0°C to 70°C.  
ꢏꢩ  
Copyright 1994, Texas Instruments Incorporated  
ꢥ ꢩ ꢦ ꢥꢞ ꢟꢳ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

SNJ54ALS323J 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS323N3 TI

完全替代

8-Bit Universal Shift/Storage Registers With Synchronous Clear And 3-State Outputs 20-PDIP
8302102RA TI

完全替代

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
SN74ALS323N TI

类似代替

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

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