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SN74ALS323N3 PDF预览

SN74ALS323N3

更新时间: 2024-11-20 21:21:03
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 117K
描述
8-Bit Universal Shift/Storage Registers With Synchronous Clear And 3-State Outputs 20-PDIP 0 to 70

SN74ALS323N3 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.37
其他特性:COMMON I/O PINS; GATED OUTPUT ENABLE INPUT计数方向:BIDIRECTIONAL
系列:ALSJESD-30 代码:R-PDIP-T20
长度:25.4 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):19 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:17 MHzBase Number Matches:1

SN74ALS323N3 数据手册

 浏览型号SN74ALS323N3的Datasheet PDF文件第2页浏览型号SN74ALS323N3的Datasheet PDF文件第3页浏览型号SN74ALS323N3的Datasheet PDF文件第4页浏览型号SN74ALS323N3的Datasheet PDF文件第5页浏览型号SN74ALS323N3的Datasheet PDF文件第6页浏览型号SN74ALS323N3的Datasheet PDF文件第7页 
SN54ALS323, SN74ALS323  
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS  
WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS  
SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994  
SN54ALS323 . . . J PACKAGE  
SN74ALS323 . . . DW OR N PACKAGE  
(TOP VIEW)  
Multiplexed I/O Ports Provide Improved Bit  
Density  
Four Modes of Operation:  
– Hold (Store)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
S0  
OE1  
OE2  
V
CC  
S1  
– Shift Right  
– Shift Left  
– Load Data  
SL  
G/Q  
Q
H  
G
Operate With Outputs Enabled or at High  
E/Q  
H/Q  
E
H
Impedance  
C/Q  
F/Q  
C
F
3-State Outputs Drive Bus Lines Directly  
Can Be Cascaded for n-Bit Word Lengths  
Synchronous Clear  
A/Q  
Q
D/Q  
B/Q  
A
D
A′  
B
CLR  
GND  
CLK  
SR  
Applications:  
– Stacked or Push-Down Registers  
– Buffer Storage  
SN54ALS323 . . . FK PACKAGE  
(TOP VIEW)  
– Accumulator Registers  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) 300-mil DIPs  
3
2
1
20 19  
18  
4
5
6
7
8
G/Q  
SL  
G
17  
16  
15  
14  
E/Q  
Q
E
C
H′  
description  
C/Q  
A/Q  
H/Q  
H
F/Q  
A
F
These 8-bit universal shift/storage registers  
feature multiplexed input/output (I/O) ports to  
achieve full 8-bit data handling in a 20-pin  
package. Two function-select (S0, S1) inputs and  
two output-enable (OE1, OE2) inputs can be used  
to choose the modes of operation listed in the  
function table.  
Q
D/Q  
D
A′  
9 10 11 12 13  
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs  
in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading  
out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs  
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has  
no effect on clearing, shifting, or storing data.  
The SN54ALS323 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74ALS323 is characterized for operation from 0°C to 70°C.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALS323N3 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54ALS323J TI

完全替代

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
8302102RA TI

完全替代

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
SN74ALS323N TI

完全替代

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

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