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SN74ALS32NSRE4 PDF预览

SN74ALS32NSRE4

更新时间: 2024-11-20 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
19页 853K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATES

SN74ALS32NSRE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SOP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.36Is Samacsys:N
系列:ALSJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:10.2 mm
逻辑集成电路类型:OR GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):4.9 mAProp。Delay @ Nom-Sup:14 ns
传播延迟(tpd):12 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

SN74ALS32NSRE4 数据手册

 浏览型号SN74ALS32NSRE4的Datasheet PDF文件第2页浏览型号SN74ALS32NSRE4的Datasheet PDF文件第3页浏览型号SN74ALS32NSRE4的Datasheet PDF文件第4页浏览型号SN74ALS32NSRE4的Datasheet PDF文件第5页浏览型号SN74ALS32NSRE4的Datasheet PDF文件第6页浏览型号SN74ALS32NSRE4的Datasheet PDF文件第7页 
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS32, SN54AS32 . . . J PACKAGE  
SN74ALS32, SN74AS32 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
1Y  
2A  
These devices contain four independent 2-input  
positive-OR gates. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2B  
2Y  
GND  
8
The  
SN54ALS32  
and  
SN54AS32  
are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS32andSN74AS32arecharacterizedfor  
operation from 0°C to 70°C.  
SN54ALS32, SN54AS32 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
X
H
L
H
X
L
H
H
L
NC  
2B  
9 10 11 12 13  
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
2
1A  
2
3
6
8
1  
3
6
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
1B  
4
4
2A  
5
2A  
5
2B  
9
2B  
3A  
10  
3B  
12  
4A  
13  
4B  
9
3A  
8
10  
3B  
11  
12  
4A  
4B  
11  
13  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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