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SN74LVTH646PWLE PDF预览

SN74LVTH646PWLE

更新时间: 2024-11-14 13:13:51
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德州仪器 - TI 总线收发器输出元件
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SN74LVTH646PWLE 数据手册

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SN54LVTH646, SN74LVTH646  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS705E – AUGUST 1997 – REVISED APRIL 1999  
SN54LVTH646 . . . JT OR W PACKAGE  
SN74LVTH646 . . . DB, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
I
and Power-Up 3-State Support Hot  
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2
off  
Insertion  
3
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
4
5
6
7
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
8
9
3.3-V V  
)
CC  
10  
11  
12  
Support Unregulated Battery Operation  
Down to 2.7 V  
B8  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
SN54LVTH646 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
4
3
2
1
28 27 26  
25  
Package Options Include Plastic  
5
A1  
A2  
A3  
NC  
A4  
A5  
A6  
OE  
B1  
B2  
NC  
B3  
B4  
B5  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Thin Very Small-Outline (DGV) Packages,  
Ceramic Chip Carriers (FK), Ceramic Flat  
(W) Package, and Ceramic (JT) DIPs  
24  
23  
22  
21  
20  
19  
6
7
8
9
10  
11  
12 13 14 15 16 17 18  
description  
These bus transceivers and registers are  
designed specifically for low-voltage (3.3-V) V  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
CC  
NC – No internal connection  
The ’LVTH646 devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B  
bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.  
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH646.  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port can be stored in either register or in both.  
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The  
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),  
A data can be stored in one register and/or B data can be stored in the other register.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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