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SN74LVTH652NSRE4 PDF预览

SN74LVTH652NSRE4

更新时间: 2024-11-14 05:24:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
18页 519K
描述
3.3V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SN74LVTH652NSRE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SOP-24针数:24
Reach Compliance Code:unknown风险等级:5.72
Is Samacsys:N其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVTJESD-30 代码:R-PDSO-G24
长度:15 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:3.5 ns
传播延迟(tpd):5.6 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:5.3 mmBase Number Matches:1

SN74LVTH652NSRE4 数据手册

 浏览型号SN74LVTH652NSRE4的Datasheet PDF文件第2页浏览型号SN74LVTH652NSRE4的Datasheet PDF文件第3页浏览型号SN74LVTH652NSRE4的Datasheet PDF文件第4页浏览型号SN74LVTH652NSRE4的Datasheet PDF文件第5页浏览型号SN74LVTH652NSRE4的Datasheet PDF文件第6页浏览型号SN74LVTH652NSRE4的Datasheet PDF文件第7页 
ꢌ ꢍꢌ ꢎꢅ ꢏꢐꢆ ꢑ ꢒꢆꢏꢄ ꢐꢓꢀ ꢆ ꢔꢏꢁꢀ ꢒꢕꢖ ꢅꢕꢔꢀ ꢏꢁꢗ ꢔꢕ ꢘ ꢖꢀ ꢆꢕ ꢔ  
SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003  
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
3.3-V V  
)
CC  
D
D
D
Support Unregulated Battery Operation  
Down to 2.7 V  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
SN54LVTH652 . . . JT OR W PACKAGE  
SN74LVTH652 . . . DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54LVTH652 . . . FK PACKAGE  
(TOP VIEW)  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKAB  
SAB  
OEAB  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
2
CLKBA  
SBA  
OEBA  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
3
4
3
2
1
28 27 26  
25  
5
6
7
8
9
4
A1  
A2  
A3  
NC  
A4  
A5  
A6  
OEBA  
B1  
B2  
NC  
B3  
B4  
24  
23  
22  
21  
20  
19  
5
6
7
8
10  
11  
9
B5  
10  
11  
12  
12 13 14 15 16 17 18  
B8  
NC − No internal connection  
description/ordering information  
These bus transceivers and registers are designed specifically for low-voltage (3.3-V) V  
the capability to provide a TTL interface to a 5-V system environment.  
operation, but with  
CC  
ORDERING INFORMATION  
ORDERABLE  
T
A
PACKAGE  
TOP-SIDE MARKING  
PART NUMBER  
SN74LVTH652DW  
SN74LVTH652DWR  
SN74LVTH652NSR  
SN74LVTH652DBR  
SN74LVTH652PW  
SN74LVTH652PWR  
SN74LVTH652DGVR  
SNJ54LVTH652JT  
SNJ54LVTH652W  
SNJ54LVTH652FK  
Tube  
SOIC − DW  
LVTH652  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH652  
LXH652  
SSOP − DB  
−40°C to 85°C  
−55°C to 125°C  
TSSOP − PW  
LXH652  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − JT  
LXH652  
SNJ54LVTH652JT  
SNJ54LVTH652W  
SNJ54LVTH652FK  
CFP − W  
Tube  
LCCC − FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢓ ꢁ ꢄꢕꢀꢀ ꢑ ꢆꢇ ꢕꢔꢙ ꢖꢀ ꢕ ꢁ ꢑꢆꢕꢗ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢚꢔ ꢑ ꢗ ꢓ ꢒꢆ ꢖꢑ ꢁ  
ꢛꢝ  
ꢦꢞ  
ꢧꢝ  
ꢆꢤꢬ  
ꢤꢥ  
ꢮꢍ  
ꢩꢦ ꢨ ꢦ ꢣ ꢤ ꢛ ꢤ ꢨ ꢞ ꢍ  
ꢤꢞ  
ꢡꢤ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVTH652NSRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH652NSR TI

完全替代

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