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SN74LVTH543

更新时间： 2024-09-08 23:09:47
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德州仪器 - TI 输出元件
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8页 127K
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3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVTH543, SN74LVTH543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS704D – AUGUST 1997 – REVISED APRIL 1999  
SN54LVTH543 . . . JT OR W PACKAGE  
SN74LVTH543 . . . DB, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
LEBA  
OEBA  
A1  
1
2
3
4
5
6
7
8
9
10  
24  
V
CC  
I
and Power-Up 3-State Support Hot  
23 CEBA  
22 B1  
21 B2  
20 B3  
19 B4  
18 B5  
17 B6  
16 B7  
off  
Insertion  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
15  
B8  
Support Unregulated Battery Operation  
Down to 2.7 V  
CEAB 11  
GND 12  
14 LEAB  
13 OEAB  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
SN54LVTH543 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
4
3
2
1 28 27 26  
25  
Package Options Include Plastic  
A2  
A3  
A4  
NC  
A5  
A6  
A7  
B2  
B3  
B4  
5
6
7
8
9
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Thin Very Small-Outline (DGV) Packages,  
Ceramic Chip Carriers (FK), Ceramic Flat  
(W) Package, and Ceramic (JT) DIPs  
24  
23  
22 NC  
B5  
21  
20 B6  
19 B7  
10  
11  
description  
12 13 14 15 16 17 18  
These octal transceivers are designedspecifically  
for low-voltage (3.3-V) V operation, but with the  
CC  
capability to provide a TTL interface to a 5-V  
system environment.  
NC – No internal connection  
The ’LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either  
direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for  
each register to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches  
inthestoragemode. WithCEABandOEABbothlow, the3-stateBoutputsareactiveandreflectthedatapresent  
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA  
inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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SN74LVTH543 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVT543 TI

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