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SN74LVTH573DW

更新时间： 2024-11-25 23:09:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 97K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74LVTH573DW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.7Is Samacsys：N
其他特性：BROADSIDE VERSION OF 373控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：LVT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：5 mA
Prop。Delay @ Nom-Sup：3.9 ns传播延迟（tpd）：4.9 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

SN74LVTH573DW 数据手册

 浏览型号SN74LVTH573DW的Datasheet PDF文件第2页浏览型号SN74LVTH573DW的Datasheet PDF文件第3页浏览型号SN74LVTH573DW的Datasheet PDF文件第4页浏览型号SN74LVTH573DW的Datasheet PDF文件第5页浏览型号SN74LVTH573DW的Datasheet PDF文件第6页浏览型号SN74LVTH573DW的Datasheet PDF文件第7页 
SN54LVTH573, SN74LVTH573  
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS687E – MAY 1997 – REVISED APRIL 1999  
SN54LVTH573 . . . J OR W PACKAGE  
SN74LVTH573 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
OE  
1D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
2D  
3D  
4D  
18 2Q  
17 3Q  
16 4Q  
3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
5D  
6D  
7D  
8D  
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
LE  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
I
and Power-Up 3-State Support Hot  
off  
GND  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
SN54LVTH573 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
3
2
1 20 19  
18  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Ceramic (J)  
DIPs  
9 10 11 12 13  
description  
These octal latches are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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SN74LVTH573DW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH573DBLE TI

完全替代

 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVTH573PW TI

完全替代

 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVTH573DBR TI

完全替代

 3.3V ABT OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS

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