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SN74LVCE161284_07

更新时间： 2024-11-02 05:16:59
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德州仪器 - TI /
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16页 336K
描述
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

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SN74LVCE161284_07 数据手册

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SN74LVCE161284  
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER  
WITH ERROR-FREE POWER UP  
www.ti.com  
SCES541–JANUARY 2004–REVISED MARCH 2005  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Auto-Power-Up Feature Prevents Printer  
Errors When Printer Is Turned On, But No  
Valid Signal Is at A9–A13 Pins  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
HD  
A9  
DIR  
Y9  
2
1.4-kΩ Pullup Resistors Integrated on All  
Open-Drain Outputs Eliminate the Need for  
Discrete Resistors  
3
A10  
A11  
A12  
A13  
Y10  
Y11  
Y12  
Y13  
4
5
Designed for IEEE Std 1284-I (Level-1 Type)  
and IEEE Std 1284-II (Level-2 Type) Electrical  
Specifications  
6
7
V
CC  
V
CC  
CABLE  
8
A1  
A2  
B1  
B2  
•
•
•
•
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
A3  
A4  
GND  
B3  
B4  
Ioff and Power-Up 3-State Support Hot  
Insertion  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A5  
B5  
A6  
GND  
A7  
B6  
GND  
B7  
ESD Protection  
– ±4 kV – Human-Body Model  
A8  
B8  
– ±8 kV – IEC 61000-4-2, Contact Discharge  
(Connector Pins)  
V
CC  
V
CC  
CABLE  
PERI LOGIC IN  
PERI LOGIC OUT  
C14  
C15  
C16  
– ±15 kV – IEC 61000-4-2, Air-Gap Discharge  
(Connector Pins)  
A14  
A15  
A16  
A17  
– ±15 kV – Human-Body Model  
(Connector Pins)  
C17  
HOST LOGIC OUT  
HOST LOGIC IN  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way  
communication between data buses. The control-function implementation minimizes external timing  
requirements.  
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR)  
is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and  
four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive  
the PERI LOGIC line.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVCE161284DL  
TOP-SIDE MARKING  
LVCE161284  
Tube  
SSOP – DL  
TSSOP – DGG  
0°C to 70°C  
Tape and reel  
Tape and reel  
SN74LVCE161284DLR  
SN74LVCE161284DGGR  
LVCE161284  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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