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SN74LVCH16240 PDF预览

SN74LVCH16240

更新时间： 2024-11-01 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
10页 151K
描述
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74LVCH16240 数据手册

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SN74LVCH16240A  
16-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS566G – MARCH 1996 – REVISED JUNE 1998  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
2OE  
1
2
3
4
5
6
7
8
9
48  
47 1A1  
46 1A2  
45 GND  
44 1A3  
43 1A4  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
V
42  
V
Power Off Disables Outputs, Permitting  
Live Insertion  
CC  
CC  
2Y1  
2Y2  
41 2A1  
40 2A2  
39 GND  
38 2A3  
37 2A4  
36 3A1  
35 3A2  
34 GND  
33 3A3  
32 3A4  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND 10  
2Y3 11  
2Y4 12  
3Y1 13  
3Y2 14  
GND 15  
3Y3 16  
3Y4 17  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
V
18  
31  
V
CC  
CC  
4Y1 19  
4Y2 20  
GND 21  
4Y3 22  
4Y4 23  
4OE 24  
30 4A1  
29 4A2  
28 GND  
27 4A3  
26 4A4  
25 3OE  
3.3-V V  
)
CC  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 16-bit buffer/driver is designed for 1.65-V to  
3.6-V V operation.  
CC  
TheSN74LVCH16240Aisdesignedspecificallytoimproveboththeperformanceanddensityof3-statememory  
address drivers, clock drivers, and bus-oriented receivers and transmitters.  
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting  
outputs and symmetrical active-low output-enable (OE) inputs.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVCH16240A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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