5秒后页面跳转
SN74LVC1G175DCKR PDF预览

SN74LVC1G175DCKR

更新时间: 2024-11-16 23:11:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
12页 226K
描述
SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR

SN74LVC1G175DCKR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:SC-70, 6 PIN针数:6
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.7Samacsys Confidence:4
Samacsys Status:ReleasedSamacsys PartID:305145
Samacsys Pin Count:6Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:DCK (R-PDSO-G6)-1
Samacsys Released Date:2017-10-06 09:34:30Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G6
JESD-609代码:e4长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:1000000 Hz最大I(ol):0.032 A
湿度敏感等级:1位数:1
功能数量:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:14.9 ns
传播延迟(tpd):15.4 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:1.25 mm最小 fmax:175 MHz
Base Number Matches:1

SN74LVC1G175DCKR 数据手册

 浏览型号SN74LVC1G175DCKR的Datasheet PDF文件第2页浏览型号SN74LVC1G175DCKR的Datasheet PDF文件第3页浏览型号SN74LVC1G175DCKR的Datasheet PDF文件第4页浏览型号SN74LVC1G175DCKR的Datasheet PDF文件第5页浏览型号SN74LVC1G175DCKR的Datasheet PDF文件第6页浏览型号SN74LVC1G175DCKR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢂ ꢉ  
ꢀꢊ ꢁꢈ ꢄ ꢋ ꢌꢍꢎ ꢏꢐ ꢋ ꢑꢄ ꢊꢐ ꢍꢑ ꢄꢒ ꢐ  
ꢓ ꢊꢎ ꢔ ꢕꢀꢏ ꢁꢆꢔꢖ ꢒꢁ ꢒꢗꢀ ꢆ ꢄꢋ ꢕꢖ  
SCES560A − MARCH 2004 − REVISED AUGUST 2004  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1
2
3
6
5
4
CLK  
GND  
D
CLR  
Inputs Accept Voltages to 5.5 V  
V
CC  
Max t of 4.3 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
Q
CC  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
I
Supports Partial-Power-Down Mode  
off  
Operation  
3 4  
2 5  
1 6  
D
GND  
CLK  
Q
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
V
CC  
CLR  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This single D-type flip-flop is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D)  
is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low  
state, regardless of the clock edge or data on D.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC1G175YEPR  
Reel of 3000  
_ _ _D6_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SN74LVC1G175YZPR  
−40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
SN74LVC1G175DBVR  
SN74LVC1G175DBVT  
SN74LVC1G175DCKR  
SOT (SOT-23) − DBV  
C75_  
D6_  
SOT (SC-70) − DCK  
Reel of 250  
SN74LVC1G175DCKT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢐꢖ ꢒ ꢌꢗ ꢆ ꢎꢊ ꢒꢁ ꢌ ꢕꢎꢕ ꢘꢙ ꢚꢛ ꢜ ꢝꢞ ꢟꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟꢘ ꢛꢙ ꢧꢞ ꢟꢣꢨ  
ꢐꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛꢜ ꢝ ꢟꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘꢛꢙ ꢠ ꢤꢣ ꢜ ꢟꢩꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢎꢣꢪ ꢞ ꢠ ꢊꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ  
ꢠ ꢟꢞ ꢙ ꢧꢞ ꢜ ꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢐꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ  
ꢟꢣ ꢠ ꢟ ꢘꢙ ꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟꢣ ꢜꢠ ꢨ  
Copyright 2004, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVC1G175DCKR 替代型号

型号 品牌 替代类型 描述 数据表
74LVC1G175DCKRG4 TI

类似代替

具有异步清零功能的单路 D 型触发器 | DCK | 6 | -40 to 125
CLVC1G175MDCKREP TI

类似代替

SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR
SN74LVC1G175DCKT TI

类似代替

SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR

与SN74LVC1G175DCKR相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC1G175DCKT TI

获取价格

SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR
SN74LVC1G175DRYR TI

获取价格

Single D-Type Flip-Flop with Asynchronous Clear 6-SON -40 to 125
SN74LVC1G175-EP TI

获取价格

SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR
SN74LVC1G175YEPR TI

获取价格

SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR
SN74LVC1G175YZPR TI

获取价格

SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR
SN74LVC1G17DBV3 TI

获取价格

SINGLE SCHMITT-TRIGGER BUFFER
SN74LVC1G17DBVE4 TI

获取价格

SINGLE SCHMITT-TRIGGER BUFFER
SN74LVC1G17DBVR TI

获取价格

SINGLE SCHMITT TRIGGER BUFFER
SN74LVC1G17DBVR UMW

获取价格

逻辑集成电路
SN74LVC1G17DBVRE4 TI

获取价格

SINGLE SCHMITT TRIGGER BUFFER