SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
FEATURES
D, DB, OR PW PACKAGE
(TOP VIEW)
•
•
•
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
V
CC
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
A
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
Y0
Y1
Y2
Y3
Y4
C
Typical VOHV (Output VOH Undershoot)
G2A
G2B
G1
> 2 V at VCC = 3.3 V, TA = 25°C
•
•
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
10 Y5
Y7
Small-Outline (D), Shrink Small-Outline (DB),
and Thin Shrink Small-Outline (PW) Packages
9
Y6
GND
DESCRIPTION
This 3-line to 8-line decoder/demultiplexer, with latches on three address inputs, is designed for 1.65-V to 3.6-V
VCC operation.
The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring
very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of this decoder and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
When the latch-enable (G2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G2A
transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further
address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the
outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2B is
high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC137A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
Y3 Y4
LATCH
ENABLE
OUTPUT
ENABLE
SELECT
G2A
X
X
L
G1
G2B
H
X
L
C
X
X
L
B
X
X
L
A
X
X
L
Y0
H
H
L
Y1
H
H
H
L
Y2
H
H
H
H
L
Y5
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
L
X
L
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
X
H
H
L
L
H
X
H
H
L
Outputs corresponding to stored address = L; all other outputs = H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the forma-
Copyright © 1994–2005, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.