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SN74LVC138A-EP PDF预览

SN74LVC138A-EP

更新时间： 2024-02-17 12:22:19
品牌 Logo 应用领域
德州仪器 - TI 解复用器
页数 文件大小 规格书
13页 612K
描述
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

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SN74LVC138A-EP 技术参数

生命周期：Active零件包装代码：SOIC
包装说明：SSOP,针数：16
Reach Compliance Code：unknown风险等级：5.71
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G16
长度：6.2 mm逻辑集成电路类型：OTHER DECODER/DRIVER
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：7.9 ns
认证状态：COMMERCIAL座面最大高度：2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：5.3 mm
Base Number Matches：1

SN74LVC138A-EP 数据手册

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SN74LVC138A-EP  
www.ti.com....................................................................................................................................... SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008  
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER  
xxx  
1
FEATURES  
•
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
D OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.8 ns at 3.3 V  
1
2
3
4
5
6
7
8
16  
15 Y0  
14  
V
A
B
CC  
Y1  
C
13 Y2  
12 Y3  
11 Y4  
10 Y5  
G2A  
G2B  
G1  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot) > 2 V at  
VCC = 3.3 V, TA = 25°C  
Y7  
9
Y6  
GND  
SUPPORTS DEFENSE, AEROSPACE,  
AND MEDICAL APPLICATIONS  
•
•
•
•
Controlled Baseline  
One Assembly/Test Site  
One Fabrication Site  
Available in Military (–55°C/125°C)  
Temperature Range(1)  
•
•
•
Extended Product Life Cycle  
Extended Product-Change Notification  
Product Traceability  
(1) Custom temperature ranges available  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.  
The device is designed for high-performance memory-decoding or data-routing applications requiring very short  
propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system  
decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder  
and the enable time of the memory usually are less than the typical access time of the memory. This means that  
the effective system delay introduced by the decoder is negligible.  
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two  
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when  
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only  
one inverter. An enable input can be used as a data input for demultiplexing applications.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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