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SN74LVC137APW PDF预览

SN74LVC137APW

更新时间： 2024-11-27 21:18:31
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 129K
描述
LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, PLASTIC, TSSOP-16

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SN74LVC137APW 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
系列：LVC/LCX/Z输入调节：LATCHED
JESD-30 代码：R-PDSO-G16长度：5 mm
逻辑集成电路类型：OTHER DECODER/DRIVER功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74LVC137APW 数据手册

 浏览型号SN74LVC137APW的Datasheet PDF文件第2页浏览型号SN74LVC137APW的Datasheet PDF文件第3页浏览型号SN74LVC137APW的Datasheet PDF文件第4页浏览型号SN74LVC137APW的Datasheet PDF文件第5页浏览型号SN74LVC137APW的Datasheet PDF文件第6页浏览型号SN74LVC137APW的Datasheet PDF文件第7页 
SN74LVC137A  
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER  
WITH ADDRESS LATCHES  
SCAS340E – MARCH 1994 – REVISED JUNE 1998  
D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
V
A
B
C
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
= 3.3 V, T = 25°C  
CC  
A
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
OH  
= 3.3 V, T = 25°C  
CC  
A
G2A  
G2B  
G1  
Y7  
GND  
Inputs Accept Voltages to 5.5 V  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This 3-line to 8-line decoder/demultiplexer with latches on three address inputs is designed for 1.65-V to 3.6-V  
operation.  
V
CC  
The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring  
very short propagation delay times. In high-performance memory systems, this decoder can be used to  
minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable  
circuit, thedelaytimesofthisdecoderandtheenabletimeofthememoryareusuallylessthanthetypicalaccess  
time of the memory. This means that the effective system delay introduced by the decoder is negligible.  
When the latch-enable (G2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G2A  
transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further  
address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the  
outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2B  
is high.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN74LVC137A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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