5秒后页面跳转
SN74LVC08AQPWREP PDF预览

SN74LVC08AQPWREP

更新时间: 2024-09-15 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
8页 114K
描述
暂无描述

SN74LVC08AQPWREP 数据手册

 浏览型号SN74LVC08AQPWREP的Datasheet PDF文件第2页浏览型号SN74LVC08AQPWREP的Datasheet PDF文件第3页浏览型号SN74LVC08AQPWREP的Datasheet PDF文件第4页浏览型号SN74LVC08AQPWREP的Datasheet PDF文件第5页浏览型号SN74LVC08AQPWREP的Datasheet PDF文件第6页浏览型号SN74LVC08AQPWREP的Datasheet PDF文件第7页 
SN54LVC08A, SN74LVC08A  
QUADRUPLE 2-INPUT POSITIVE-AND GATES  
SCAS283G – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC08A . . . J OR W PACKAGE  
SN74LVC08A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
2Y  
GND  
= 3.3 V, T = 25°C  
CC  
A
8
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Inputs Accept Voltages to 5.5 V  
SN54LVC08A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flat (W) Packages, and DIPs (J)  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
description  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
The SN54LVC08A quadruple 2-input positive-  
3B  
AND gate is designed for 2.7-V to 3.6-V V  
CC  
operation and the SN74LVC08A quadruple  
2-input positive-AND gate is designed for 1.65-V  
to 3.6-V V  
operation.  
CC  
NC – No internal connection  
The ’LVC08A devices perform the Boolean  
Y
A B or Y  
A
B
in positive  
function  
logic.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC08A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVC08A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
H
L
L
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVC08AQPWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC08AMPWREP TI

完全替代

暂无描述
SN74LVC08AMDREP TI

类似代替

增强型产品 4 通道、2 输入、2V 至 3.6V 与门 | D | 14 | -55 t
SN74LVC08AQPWRQ1 TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-AND GATE

与SN74LVC08AQPWREP相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC08AQPWRG4Q1 TI

获取价格

汽车类 4 通道、2 输入、2V 至 3.6V 与门 | PW | 14 | -40 to
SN74LVC08AQPWRQ1 TI

获取价格

QUADRUPLE 2-INPUT POSITIVE-AND GATE
SN74LVC08ARGYR TI

获取价格

QUADRUPLE 2-INPUT POSITIVE-AND GATES
SN74LVC08ARGYRG4 TI

获取价格

QUADRUPLE 2-INPUT POSITIVE-AND GATES
SN74LVC08PW TI

获取价格

8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT
SN74LVC10A TI

获取价格

TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74LVC10AD TI

获取价格

TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74LVC10ADB TI

获取价格

TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74LVC10ADBLE TI

获取价格

TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74LVC10ADBR TI

获取价格

TRIPLE 3-INPUT POSITIVE-NAND GATE