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ꢋ ꢍꢉꢎꢏ ꢍꢐꢄ ꢑ ꢒ ꢊꢓꢁ ꢐꢍꢔ ꢐꢕ ꢀꢓ ꢔ ꢓꢅꢑ ꢊꢉꢁ ꢎ ꢖ ꢉꢔꢑ
SCES480B − AUGUST 2003 − REVISED MAY 2004
D
Qualification in Accordance With
AEC-Q100
D
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
†
= 3.3 V, T = 25°C
CC A
D
Qualified for Automotive Applications
D
Typical V
(Output V
Undershoot)
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D OR PW PACKAGE
(TOP VIEW)
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2A
2B
2Y
V
CC
4B
4A
4Y
3B
3A
3Y
D
D
D
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t of 4.1 ns at 3.3 V
pd
†
Contact factory for details. Q100 qualification data available on
request.
8
GND
description/ordering information
The SN74LVC08A-Q1 quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V V
operation.
CC
Y + A • B or Y + A ) B
The device performs the Boolean function
in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Reel of 2500
Reel of 2000
SN74LVC08AQDRQ1
SN74LVC08AQPWRQ1
LVC08AQ
LVC08AQ
−40°C to 125°C
TSSOP − PW
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
H
L
L
X
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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