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SN74LV174DR PDF预览

SN74LV174DR

更新时间: 2024-11-02 09:13:31
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
8页 155K
描述
HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN74LV174DR 数据手册

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SN54LV174, SN74LV174  
HEX D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS192B – FEBRUARY 1993 – REVISED APRIL 1996  
SN54LV174 . . . J OR W PACKAGE  
SN74LV174 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
6Q  
6D  
5D  
5Q  
4D  
4Q  
CLK  
OHV  
CC  
OH  
1D  
2D  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2Q  
3D  
3Q  
GND  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV174 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18 6D  
1D  
2D  
NC  
2Q  
3D  
4
5
6
7
8
description  
17  
16  
15  
14  
5D  
NC  
5Q  
4D  
These hex D-type flip-flops are designed for 2.7-V  
to 5.5-V V operation.  
CC  
The ’LV174 are monolithic positive-edge-  
triggered flip-flops with a direct clear (CLR) input.  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a particular  
9 10 11 12 13  
NC – No internal connection  
voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When  
the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.  
The SN74LV174 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV174 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV174 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
L
H
L
H
H
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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