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SN74LV174PWLE PDF预览

SN74LV174PWLE

更新时间： 2024-11-02 09:13:31
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 155K
描述
HEX D-TYPE FLIP-FLOPS WITH CLEAR

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SN74LV174PWLE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.48系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G16长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：30000000 Hz最大I（ol）：0.006 A
位数：6功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：29 ns传播延迟（tpd）：36 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：90 MHz
Base Number Matches：1

SN74LV174PWLE 数据手册

 浏览型号SN74LV174PWLE的Datasheet PDF文件第2页浏览型号SN74LV174PWLE的Datasheet PDF文件第3页浏览型号SN74LV174PWLE的Datasheet PDF文件第4页浏览型号SN74LV174PWLE的Datasheet PDF文件第5页浏览型号SN74LV174PWLE的Datasheet PDF文件第6页浏览型号SN74LV174PWLE的Datasheet PDF文件第7页 
SN54LV174, SN74LV174  
HEX D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS192B – FEBRUARY 1993 – REVISED APRIL 1996  
SN54LV174 . . . J OR W PACKAGE  
SN74LV174 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
6Q  
6D  
5D  
5Q  
4D  
4Q  
CLK  
OHV  
CC  
OH  
1D  
2D  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2Q  
3D  
3Q  
GND  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV174 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18 6D  
1D  
2D  
NC  
2Q  
3D  
4
5
6
7
8
description  
17  
16  
15  
14  
5D  
NC  
5Q  
4D  
These hex D-type flip-flops are designed for 2.7-V  
to 5.5-V V operation.  
CC  
The ’LV174 are monolithic positive-edge-  
triggered flip-flops with a direct clear (CLR) input.  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a particular  
9 10 11 12 13  
NC – No internal connection  
voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When  
the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.  
The SN74LV174 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV174 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV174 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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