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SN74LV175APWRE4 PDF预览

SN74LV175APWRE4

更新时间: 2024-11-25 05:17:07
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
15页 362K
描述
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN74LV175APWRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:45000000 Hz
最大I(ol):0.006 A湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:17 ns传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:125 MHzBase Number Matches:1

SN74LV175APWRE4 数据手册

 浏览型号SN74LV175APWRE4的Datasheet PDF文件第2页浏览型号SN74LV175APWRE4的Datasheet PDF文件第3页浏览型号SN74LV175APWRE4的Datasheet PDF文件第4页浏览型号SN74LV175APWRE4的Datasheet PDF文件第5页浏览型号SN74LV175APWRE4的Datasheet PDF文件第6页浏览型号SN74LV175APWRE4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁꢇ ꢃꢄꢅ ꢆꢇ ꢂꢈ  
ꢊ ꢋꢈꢌꢍ ꢋꢎꢄ ꢏ ꢌꢐꢑ ꢒꢎ ꢏ ꢓ ꢄ ꢔꢎ ꢐ ꢓꢄꢕ ꢎ ꢀ  
ꢖ ꢔꢑꢗ ꢘ ꢄꢏ ꢈꢍ  
SCLS400G − APRIL 1998 − REVISED APRIL 2005  
SN54LV175A . . . J OR W PACKAGE  
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 7.5 ns at 5 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
CLR  
1Q  
1Q  
1D  
2D  
2Q  
2Q  
GND  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
A
4Q  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
Contain Four Flip-Flops With Double-Rail  
Outputs  
Applications Include:  
− Buffer/Storage Registers  
− Shift Registers  
SN54LV175A . . . FK PACKAGE  
(TOP VIEW)  
− Pattern Generators  
D
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
3
2 1 20 19  
18 4Q  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
1Q  
1D  
NC  
2D  
2Q  
4
5
6
7
8
17  
4D  
NC  
3D  
3Q  
16  
15  
14  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
9 10 11 12 13  
The ’LV175A devices are quadruple D-type  
flip-flops designed for 2-V to 5.5-V V  
operation.  
CC  
NC − No internal connection  
These devices have a direct clear (CLR) input and  
feature complementary outputs from each  
flip-flop.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube of 40  
SN74LV175AD  
SOIC − D  
LV175A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV175ADR  
SN74LV175ANSR  
SN74LV175ADBR  
SN74LV175APW  
SN74LV175APWR  
SN74LV175APWT  
SN74LV175ADGVR  
SNJ54LV175AJ  
SOP − NS  
74LV175A  
LV175A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV175A  
TVSOP − DGV  
CDIP − J  
LV175A  
SNJ54LV175AJ  
SNJ54LV175AW  
SNJ54LV175AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV175AW  
SNJ54LV175AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢋ ꢁ ꢄꢏꢀꢀ ꢕ ꢑꢗ ꢏꢍꢖ ꢔꢀ ꢏ ꢁ ꢕꢑꢏꢌ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢎꢍ ꢕ ꢌ ꢋ ꢘꢑ ꢔꢕ ꢁ  
ꢧꢤ ꢦ ꢤ ꢡ ꢢ ꢙ ꢢ ꢦ ꢜ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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