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SN74LV175ANSE4 PDF预览

SN74LV175ANSE4

更新时间： 2024-02-17 07:29:57
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 208K
描述
LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOP-16

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SN74LV175ANSE4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.41Is Samacsys：N
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
逻辑集成电路类型：D FLIP-FLOP湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260传播延迟（tpd）：27 ns
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：125 MHz
Base Number Matches：1

SN74LV175ANSE4 数据手册

 浏览型号SN74LV175ANSE4的Datasheet PDF文件第2页浏览型号SN74LV175ANSE4的Datasheet PDF文件第3页浏览型号SN74LV175ANSE4的Datasheet PDF文件第4页浏览型号SN74LV175ANSE4的Datasheet PDF文件第5页浏览型号SN74LV175ANSE4的Datasheet PDF文件第6页浏览型号SN74LV175ANSE4的Datasheet PDF文件第7页 
SN54LV175A, SN74LV175A  
QUADRUPLE D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS400C – APRIL 1998 – REVISED MAY 2000  
SN54LV175A . . . J OR W PACKAGE  
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
4Q  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
1Q  
1D  
A
2-V to 5.5-V V  
Operation  
CC  
2D  
2Q  
Support Mixed-Mode Voltage Operation on  
All Ports  
2Q  
GND  
Contain Four Flip-Flops With Double-Rail  
Outputs  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
SN54LV175A . . . FK PACKAGE  
(TOP VIEW)  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
3
2 1 20 19  
18 4Q  
1Q  
1D  
NC  
2D  
2Q  
4
5
6
7
8
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
17  
4D  
NC  
3D  
3Q  
16  
15  
14  
Package Options Include Plastic  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), and  
Thin Shrink Small-Outline (PW) Packages,  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and DIPs (J)  
9 10 11 12 13  
NC – No internal connection  
description  
The ’LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V V  
operation.  
CC  
These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the  
positive-going edge of the clock (CLK) pulse.  
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the  
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.  
The SN54LV175A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV175A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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