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SN74LV165APWE4 PDF预览

SN74LV165APWE4

更新时间: 2024-11-03 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
17页 470K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SN74LV165APWE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.2
其他特性:SISO OPERATION ALSO AVAILABLE计数方向:RIGHT
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT最大频率@ Nom-Sup:50000000 Hz
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V传播延迟(tpd):26 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Shift Register最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:45 MHzBase Number Matches:1

SN74LV165APWE4 数据手册

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ꢋꢈꢌꢈ ꢄꢄ ꢍꢄ ꢎꢄ ꢏ ꢈꢐ ꢑ ꢎꢒꢓ ꢔ ꢀꢕ ꢓꢖ ꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌ ꢀ  
SCLS402K − APRIL 1998 − REVISED APRIL 2005  
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
CC  
Max t of 10.5 ns at 5 V  
pd  
Support Mixed-Mode Voltage Operation on  
All Ports  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
I
Supports Partial-Power-Down Mode  
off  
− 1000-V Charged-Device Model (C101)  
Operation  
SN54LV165A . . . J OR W PACKAGE  
SN74LV165A . . . D, DB, DGV, NS,  
OR PW PACKAGE  
SN74LV165A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV165A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SH/LD  
CLK  
E
V
CC  
CLK INH  
1
16  
CLK  
E
F
G
H
Q
H
15  
14  
13  
12  
11  
10  
2
3
4
5
6
7
CLK INH  
D
C
B
A
SER  
3
2
1
20 19  
18  
D
C
B
A
4
5
6
7
8
D
C
NC  
B
A
E
F
NC  
G
F
G
H
17  
16  
15  
14  
Q
SER  
H
H
9 10 11 12 13  
GND  
Q
H
8
9
NC − No internal connection  
description/ordering information  
The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V V  
operation.  
CC  
When the devices are clocked, data is shifted toward the serial output Q . Parallel-in access to each stage is  
H
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.  
The ’LV165A devices feature a clock-inhibit function and a complemented serial output, Q .  
H
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Reel of 1000  
Tube of 40  
SN74LV165ARGYR  
SN74LV165AD  
LV165A  
LV165A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV165ADR  
SN74LV165ANSR  
SN74LV165ADBR  
SN74LV165APW  
SN74LV165APWR  
SN74LV165APWT  
SN74LV165ADGVR  
SNJ54LV165AJ  
SOP − NS  
74LV165A  
LV165A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV165A  
TVSOP − DGV  
CDIP − J  
LV165A  
SNJ54LV165AJ  
SNJ54LV165AW  
SNJ54LV165AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV165AW  
SNJ54LV165AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢘ ꢁ ꢄꢍꢀꢀ ꢏ ꢔꢕ ꢍꢌꢙ ꢓꢀ ꢍ ꢁ ꢏꢔꢍꢐ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢋꢌ ꢏ ꢐ ꢘ ꢦꢔ ꢓꢏ ꢁ  
ꢨꢢ  
ꢣꢤ  
ꢥꢨ  
ꢯꢬ  
ꢩꢥ ꢨ ꢥ ꢢ ꢣ ꢚ ꢣ ꢨ ꢝ ꢬ  
ꢣꢝ  
ꢝꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LV165APWE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV165APWTG4 TI

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PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LV165APWR TI

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PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LV165APW TI

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PARALLEL-LOAD 8-BIT SHIFT REGISTERS

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