SN74LV165B-EP
SCES954 – JANUARY 2023
SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift
Registers
1 Features
3 Description
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2 V to 5.5 V VCC operation
The SN74LV165B-EP device is a parallel-load, 8-bit
shift registers designed for 2 V to 5.5 V VCC operation.
Maximum tpd of 10.5 ns at 5 V
Supports mixed-mode voltage operation on all
ports
Ioff supports partial-power-down mode operation
Latch-up performance exceeds 250 mA per JESD
17
Operating ambient temperature: -55°C to +125°C
Supports defense, aerospace, and medical
applications:
When the device is clocked, data is shifted toward the
serial output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs that are
enabled by a low level at the shift/load (SH/ LD) input.
The SN74LV165B-EP devices features a clock-inhibit
function and a complemented serial output, Q H.
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This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow
through the devices when they are powered down.
– Controlled baseline
– One assembly and test site
– One fabrication site
– Extended product life cycle
– Extended product-change notification
– Product traceability
Package Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LV165B-EP PW (TSSOP, 16)
5.00 mm × 4.40 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
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Increase the number of inputs on a microcontroller
A
H
B
C
D
E
F
G
SH/LD
5 Additional
Shift Register
Stages
S
D
R
Q
S
D
R
Q
S
D
R
Q
Q
QH
QH
SER
CLK INH
CLK
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.