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ꢋ
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
D
D
D
2-V to 5.5-V V
Operation
D
D
D
Direct Overriding Clear
CC
Max t of 10.5 ns at 5 V
Parallel-to-Serial Conversion
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
OLP
CC
= 3.3 V, T = 25°C
A
D
D
D
Typical V
>2.3 V at V
(Output V
Undershoot)
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
OHV
CC
OH
= 3.3 V, T = 25°C
A
I
Supports Partial-Power-Down-Mode
off
− 1000-V Charged-Device Model (C101)
Operation
Synchronous Load
SN54LV166A . . . J OR W PACKAGE
SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV166A . . . FK PACKAGE
(TOP VIEW)
SER
V
CC
SH/LD
H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
3
2
1 20 19
18
B
C
H
Q
B
4
5
6
7
8
Q
H
G
C
NC
17
16
15
14
H
D
NC
G
CLK INH
CLK
F
D
E
F
CLK INH
9 10 11 12 13
GND
CLR
NC − No internal connection
description/ordering information
The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 40
SN74LV166AD
SOIC − D
LV166A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV166ADR
SN74LV166ANSR
SN74LV166ADBR
SN74LV166APW
SN74LV166APWR
SN74LV166APWT
SN74LV166ADGVR
SNJ54LV166AJ
SOP − NS
74LV166A
LV166A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV166A
TVSOP − DGV
CDIP − J
LV166A
SNJ54LV166AJ
SNJ54LV166AW
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV166AW
SNJ54LV166AFK
LCCC − FK
SNJ54LV166AFK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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1
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