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SN74LV165DBLE PDF预览

SN74LV165DBLE

更新时间： 2024-09-15 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 168K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

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中文翻译

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SN74LV165DBLE 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SSOP-16针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.79Is Samacsys：N
其他特性：CLOCK INHIBIT计数方向：RIGHT
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G16
长度：6.2 mm负载电容（CL）：50 pF
逻辑集成电路类型：PARALLEL IN SERIAL OUT最大频率@ Nom-Sup：24000000 Hz
位数：8功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V传播延迟（tpd）：47 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：Shift Registers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：90 MHz
Base Number Matches：1

SN74LV165DBLE 数据手册

 浏览型号SN74LV165DBLE的Datasheet PDF文件第2页浏览型号SN74LV165DBLE的Datasheet PDF文件第3页浏览型号SN74LV165DBLE的Datasheet PDF文件第4页浏览型号SN74LV165DBLE的Datasheet PDF文件第5页浏览型号SN74LV165DBLE的Datasheet PDF文件第6页浏览型号SN74LV165DBLE的Datasheet PDF文件第7页 
SN54LV165, SN74LV165  
PARALLEL-LOAD 8-BIT SHIFT REGISTERS  
SCES007B – MARCH 1995 – REVISED APRIL 1996  
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
SN54LV165 . . . J OR W PACKAGE  
SN74LV165 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
SH/LD  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Typical V  
< 2 V at V , T = 25°C  
(Output V  
Undershoot)  
OHV  
CC  
OH  
CLK  
E
CLK INH  
D
A
ESDProtectionExceeds2000VPer  
MIL-STD-883C,Method3015;Exceeds200V  
UsingMachineModel(C=200pF, R=0)  
F
C
G
B
H
A
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
Q
SER  
H
GND  
Q
H
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV165 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
The ’LV165 parallel-load, 8-bit shift registers are  
designed for 2.7-V to 5.5-V V operation.  
D
4
5
6
7
8
E
F
CC  
17  
16  
15  
14  
C
When the device is clocked, data is shifted toward  
NC  
B
NC  
G
the serial output Q . Parallel-in access to each  
H
stage is provided by eight individual direct data  
inputs that are enabled by a low level at the SH/LD  
input. The ’LV165 feature a clock inhibit function  
A
H
9 10 11 12 13  
and a complemented serial output Q .  
H
Clocking is accomplished by a low-to-high  
transition of the clock (CLK) input while SH/LD is  
NC – No internal connection  
held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are  
interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK  
INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held  
high. The parallel inputs to the register are enabled while SH/LD is held low independently of the levels of CLK,  
CLK INH, or SER.  
The SN54LV165 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV165 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
SH/LD  
CLK  
X
CLK INH  
L
X
X
H
↑
Parallel load  
H
H
H
H
H
Q
Q
0
0
X
L
Shift  
Shift  
↑
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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