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SN74LV07APWLE PDF预览

SN74LV07APWLE

更新时间： 2024-11-25 05:29:19
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
6页 103K
描述
LV/LV-A/LVX/H SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14, TSSOP-14

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SN74LV07APWLE 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.33系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G14长度：5 mm
逻辑集成电路类型：BUFFER功能数量：6
输入次数：1端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：OPEN-DRAIN封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：18 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mm

SN74LV07APWLE 数据手册

 浏览型号SN74LV07APWLE的Datasheet PDF文件第2页浏览型号SN74LV07APWLE的Datasheet PDF文件第3页浏览型号SN74LV07APWLE的Datasheet PDF文件第4页浏览型号SN74LV07APWLE的Datasheet PDF文件第5页浏览型号SN74LV07APWLE的Datasheet PDF文件第6页 
SN54LV07A, SN74LV07A  
HEX BUFFERS/DRIVERS  
WITH OPEN-DRAIN OUTPUTS  
SCES337C – MAY 2000 – REVISED AUGUST 2000  
SN54LV07A . . . J OR W PACKAGE  
SN74LV07A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
2-V to 5.5-V V  
Operation  
CC  
1A  
1Y  
2A  
2Y  
3A  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Typical V  
OLP  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
CC  
6A  
6Y  
5A  
5Y  
4A  
4Y  
<0.8 V at V  
CC  
A
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Outputs Are Disabled During Power Up and  
Power Down With Inputs Tied to V  
3Y  
GND  
CC  
8
Support Mixed-Mode Voltage Operation on  
All Ports  
SN54LV07A . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
3
2
1 20 19  
18  
6Y  
NC  
5A  
NC  
5Y  
2A  
NC  
2Y  
4
5
6
7
8
– 1000-V Charged-Device Model (C101)  
17  
16  
15  
14  
Package Options Include Plastic  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and DIPs (J)  
NC  
3A  
9 10 11 12 13  
description  
NC – No internal connection  
These hex buffers/drivers are designed for 2-V to  
5.5-V V operation.  
CC  
The ’LV07A devices perform the Boolean function  
Y = A in positive logic.  
The open-drain outputs require pullup resistors to perform correctly and can be connected to other open-drain  
outputs to implement active-low wired-OR or active-high wired-AND functions.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the devices when they are powered down.  
The SN54LV07A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV07A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer/driver)  
INPUT  
A
OUTPUT  
Y
H
L
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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