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SN74LV08ADBE4 PDF预览

SN74LV08ADBE4

更新时间: 2024-11-04 15:52:19
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
7页 124K
描述
LV/LV-A/LVX/H SERIES, QUAD 2-INPUT AND GATE, PDSO14

SN74LV08ADBE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:SSOP,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.77系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:6.2 mm逻辑集成电路类型:AND GATE
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):20 ns
认证状态:Not Qualified座面最大高度:2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

SN74LV08ADBE4 数据手册

 浏览型号SN74LV08ADBE4的Datasheet PDF文件第2页浏览型号SN74LV08ADBE4的Datasheet PDF文件第3页浏览型号SN74LV08ADBE4的Datasheet PDF文件第4页浏览型号SN74LV08ADBE4的Datasheet PDF文件第5页浏览型号SN74LV08ADBE4的Datasheet PDF文件第6页浏览型号SN74LV08ADBE4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄꢅ ꢆꢇ  
ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢑ ꢒꢓꢁ ꢏꢋꢔ ꢏꢕ ꢀꢓ ꢔ ꢓꢅꢐ ꢒꢌꢁ ꢍ ꢖ ꢌꢔꢐ ꢀ  
SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV08 . . . J OR W PACKAGE  
SN74LV08 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
(Output V  
Undershoot)  
4B  
4A  
4Y  
OHV  
OH  
> 2 V at V , T = 25°C  
1Y  
CC  
A
2A  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2B  
10 3B  
9
8
2Y  
3A  
3Y  
GND  
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV08 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and Ceramic (J) 300-mil DIPs  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
description  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
These quadruple 2-input positive-AND gates are  
designed for 2.7-V to 5.5-V V operation.  
3B  
CC  
The ’LV08 perform Boolean function Y = A B or  
Y = in positive logic.  
A ) B  
NC − No internal connection  
The SN74LV08 is available in TI’s shrink  
small-outline package (DB), which provides the  
same I/O pin count and functionality of standard  
small-outline packages in less than half the  
printed-circuit-board area.  
The SN54LV08 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74LV08 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
H
L
L
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
ꢋ ꢁ ꢄꢐꢀꢀ ꢕ ꢔꢗ ꢐꢎꢘ ꢓꢀ ꢐ ꢁ ꢕꢔꢐꢍ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢏꢎ ꢕ ꢍ ꢋ ꢥꢔ ꢓꢕ ꢁ  
ꢨꢤ ꢧ ꢤ ꢡ ꢢ ꢙ ꢢ ꢧ ꢜ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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