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SN74LV08ADBRG4 PDF预览

SN74LV08ADBRG4

更新时间: 2024-11-21 05:17:11
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德州仪器 - TI 输入元件
页数 文件大小 规格书
18页 799K
描述
QUADRUPLE2-INPUT POSITIVE-AND GATES

SN74LV08ADBRG4 数据手册

 浏览型号SN74LV08ADBRG4的Datasheet PDF文件第2页浏览型号SN74LV08ADBRG4的Datasheet PDF文件第3页浏览型号SN74LV08ADBRG4的Datasheet PDF文件第4页浏览型号SN74LV08ADBRG4的Datasheet PDF文件第5页浏览型号SN74LV08ADBRG4的Datasheet PDF文件第6页浏览型号SN74LV08ADBRG4的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ  
SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005  
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 7 ns at 5 V  
pd  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
− 1000-V Charged-Device Model (C101)  
SN54LV08A . . . J OR W PACKAGE  
SN74LV08A . . . D, DB, DGV, NS,  
OR PW PACKAGE  
SN74LV08A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV08A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
14  
1A  
1B  
V
3
2
1
20 19  
18  
1
2
3
4
5
6
7
14  
CC  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
1B  
1Y  
2A  
2B  
2Y  
13 4B  
12 4A  
2
3
4
5
6
13 4B  
17  
16  
12  
11  
10  
9
1Y  
4A  
4Y  
3B  
3A  
3Y  
11  
10  
9
4Y  
3B  
3A  
2A  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
2B  
3B  
2Y  
7
8
8
GND  
NC − No internal connection  
description/ordering information  
These quadruple 2-input positive-AND gates are designed for 2-V to 5.5-V V  
operation. The ’LV08A devices  
CC  
Y + A B or Y + A ) B  
perform the Boolean function  
in positive logic.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the devices when they are powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Reel of 1000  
Tube of 50  
SN74LV08ARGYR  
SN74LV08AD  
LV08A  
LV08A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV08ADR  
SN74LV08ANSR  
SN74LV08ADBR  
SN74LV08APW  
SN74LV08APWR  
SN74LV08APWT  
SN74LV08ADGVR  
SNJ54LV08AJ  
SOP − NS  
74LV08A  
LV08A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV08A  
TVSOP − DGV  
CDIP − J  
LV08A  
SNJ54LV08AJ  
SNJ54LV08AW  
SNJ54LV08AFK  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV08AW  
SNJ54LV08AFK  
−55°C to 125°C  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢌ ꢁ ꢄꢐꢀꢀ ꢕ ꢔꢗ ꢐꢎꢘ ꢓꢀ ꢐ ꢁ ꢕꢔꢐꢍ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢏꢎ ꢕ ꢍ ꢌ ꢥꢔ ꢓꢕ ꢁ  
ꢤꢧ  
ꢮꢫ  
ꢨꢤ ꢧ ꢤ ꢡ ꢢ ꢙ ꢢ ꢧ ꢜ ꢫ  
ꢢꢜ  
ꢜꢙ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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