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SN74LS322AJDS PDF预览

SN74LS322AJDS

更新时间: 2024-12-01 12:59:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
4页 118K
描述
Parallel In Parallel Out, LS Series, 8-Bit, Right Direction, True Output, TTL, CDIP20, CERAMIC, DIP-20

SN74LS322AJDS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
其他特性:COMMON I/O PINS; SIGN EXTEND FUNCTION; TOTEMPOLE SERIAL SHIFT RIGHT OUTPUT计数方向:RIGHT
系列:LSJESD-30 代码:R-CDIP-T20
JESD-609代码:e0长度:24.515 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:25000000 Hz
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Shift Registers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:35 MHz
Base Number Matches:1

SN74LS322AJDS 数据手册

 浏览型号SN74LS322AJDS的Datasheet PDF文件第2页浏览型号SN74LS322AJDS的Datasheet PDF文件第3页浏览型号SN74LS322AJDS的Datasheet PDF文件第4页 
SN54/74LS322A  
8-BIT SHIFT REGISTERS  
WITH SIGN EXTEND  
These 8-bit shift registers have multiplexed input/output data ports to  
accomplish full 8-bit data handling in a single 20-pin package. Serial data may  
enter the shift-right register through either D0 or D1 inputs as selected by the  
data select pin. A serial output is also provided. Synchronous parallel loading  
is achieved by taking the register enable and the S/P inputs low. This places  
the three-state input/output ports in the data input mode. Data is entered on  
the low-to-high clock transition. The data extend function repeats the sign in  
8-BIT SHIFT REGISTERS  
WITH SIGN EXTEND  
LOW POWER SCHOTTKY  
the Q flip-flop during shifting. An overriding clear input clears the internal  
A
registers when taken low whether the outputs are enabled or off. The output  
enable does not affect synchronous operation of the register.  
Multiplexed Inputs/Outputs Provide Improved Bit Density  
Sign Extend Function  
J SUFFIX  
CERAMIC  
Direct Overriding Clear  
3-State Outputs Drive Bus Lines Directly  
CASE 732-03  
20  
1
(TOP VIEW)  
DATA  
SIGN  
N SUFFIX  
PLASTIC  
CASE 738-03  
V
SELECT EXTEND D1  
B/Q  
D/Q  
F/Q  
H/Q  
Q/  
H
CLOCK  
11  
CC  
B
D
F
H
19  
DS  
18  
SE  
17  
D1  
16  
15  
14  
13  
12  
20  
20  
1
B/Q  
D/Q  
F/Q  
H/G  
Q/  
B
D
F
H
H
G
CK  
DW SUFFIX  
SOIC  
CASE 751D-03  
S/P  
D0  
A/Q C/Q  
E/Q  
G/Q  
7
OE  
8
CLR  
A
C
E
G
20  
1
1
2
3
4
5
6
9
10  
REGISTER S/P  
ENABLE  
D0  
A/Q  
C/Q  
E/Q  
E
G/Q OUTPUT CLEAR GND  
G
A
C
ENABLE  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
GUARANTEED OPERATING RANGES  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
V
CC  
Supply Voltage  
54  
74  
4.5  
4.75  
5.0  
5.0  
5.5  
5.25  
V
T
A
Operating Ambient Temperature Range  
54  
74  
55  
0
25  
25  
125  
70  
°C  
I
I
Output Current — High  
Output Current — Low  
Q
54, 74  
0.4  
mA  
mA  
OH  
H
Q
Q
54  
74  
4.0  
8.0  
OL  
H
H
I
I
Output Current — High  
Output Current — Low  
Q Q  
Q Q  
A
54  
74  
1.0  
2.6  
mA  
mA  
OH  
A
H
H
Q Q  
54  
74  
12  
24  
OL  
A
H
H
Q Q  
A
FAST AND LS TTL DATA  
5-1  

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